{"id":2570177,"url":"https://alion.io/job/tylsemi-rtl-design-engineer","title":"RTL Design Engineer","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"B","score":75,"open_postings":20,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":["IN"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":45000,"period":"year","method":"role_seniority_country_cell","sample_n":14},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Formal Verification","optional":true},{"name":"OpenAI","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"closed","first_seen_at":"2026-06-01T10:27:30Z","employer_posted_date":"2026-06-01","last_verified_at":"2026-10-15T17:45:50Z","board_verified":false,"closed_at":"2026-10-15T17:45:50Z","days_open":136,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":135},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nTylSemi Solutions Private Limited is seeking a talented and motivated Senior RTL Design Engineer to join our growing semiconductor design team. In this role, you will be responsible for the design and development of high-performance digital IPs and SoC components for next-generation AI, HPC, and Networking applications. You will work closely with architecture, verification, physical design, and software teams to deliver robust and scalable silicon solutions.\nWhat You'll Do\nDevelop RTL designs using Verilog/System Verilog based on architectural and microarchitecture specifications.\nParticipate in microarchitecture definition and design reviews.\nImplement high-performance, area-efficient, and power-optimized digital logic.\nDevelop and maintain design documentation, specifications, and implementation guidelines.\nCollaborate with verification engineers to define verification strategies and debug functional issues.\nPerform RTL simulations and support design validation activities.\nAnalyze synthesis results and work with physical design teams to optimize timing, power, and area.\nSupport SoC integration activities and resolve integration-related issues.\nParticipate in design reviews, code reviews, and quality improvement initiatives.\nWork closely with cross-functional teams throughout the ASIC development lifecycle.\nRequired Qualifications\nBachelor's or master's degree in electrical engineering, Electronics Engineering, Computer Engineering, or related field.\n5+years experience in RTL design and digital IC development.\nStrong understanding of digital design fundamentals, computer architecture, and ASIC design flow.\nProficiency in:\nVerilog/System Verilog\nRTL design and coding methodologies\nLogic design and finite state machines (FSMs)\nClock domain crossing (CDC) concepts\nLow-power design fundamentals\n\nExperience with simulation and debugging tools.\nFamiliarity with synthesis and timing analysis concepts.\nStrong analytical and problem-solving skills.\nPreferred Qualifications\nExperience designing IPs or subsystems for AI, HPC, Networking, or data-center applications.\nKnowledge of industry-standard protocols such as:\nAXI/AHB/APB\nPCIe\nDDR\nEthernet\nCXL\nUCIe\n\nFamiliarity with scripting languages such as Python, Perl, Shell, or TCL.\nExposure to low-power design methodologies and power intent formats (UPF/CPF).\nUnderstanding of linting, CDC, RDC, and formal verification tools.\nExperience with FPGA prototyping is a plus.\nKey Attributes\nStrong attention to detail and commitment to design quality.\nPassion for semiconductor innovation and cutting-edge technologies.\nExcellent debugging and problem-solving abilities.\nAbility to work effectively in a collaborative and fast-paced environment.\nStrong communication and teamwork skills.\nOwnership mindset with a focus on delivering high-quality silicon.","description_format":"text","description_chars":5948,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Design & 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