{"id":3153620,"url":"https://alion.io/job/tylsemi-senior-staff-design-verification-engineer","title":"Senior Staff - Design Verification Engineer","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":90,"open_postings":12,"ghost_share":0,"stale_share":0.417,"repost_share":0,"time_to_fill_p50_days":55,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"AI Agents","optional":true},{"name":"Anomaly Detection","optional":true},{"name":"OpenAI","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-21T03:17:27Z","employer_posted_date":"2026-08-21","last_verified_at":"2026-11-03T12:38:33Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":74},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe are seeking a highly experienced Senior Staff - Design Verification engineer to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications. This role requires deep expertise in verifying large and complex SoCs and a passion for building next-gen verification platforms, leveraging automation, portability, and AI-driven methodologies.\nWhat You’ll Do\nDefine and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP → subsystem → full SoC level\nArchitect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs \nEstablish methodologies for seamless reuse and portability, including Portable Stimulus (PSS) -based verification flows \nLead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM) \nDrive multi-level verification strategies, enabling efficient scaling across: \nBlock-level, Multi-block/subsystem level, Full-chip SoC level \nDefine and enforce verification quality metrics, coverage closure strategies, and sign-off criteria \nChampion a “fail-fast” philosophy to detect issues early and improve overall design quality \nDrive initiatives toward first-pass silicon success, minimizing escapes and post-silicon debug effort \nLeverage AI/ML techniques and AI agents to: \nAutomate testbench generation \nImprove stimulus generation and coverage closure \nEnhance regression efficiency and debug productivity \nEnable intelligent verification QA and anomaly detection \nCollaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection \nMentor and guide DV teams on best practices,methodologyadoption, and architectural decisions\nWhat We’re Looking For\nBachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field \n12 to 16 years of experience in Design Verification, with significant exposure to large SoC verification\nProven experience in defining and deploying verification architectures for complex chips\nStrong expertise in: \nSystemVerilog and UVM \nCoverage-driven verification (functional + code coverage) \nAssertion-based verification (SVA) \nHands-on experience with Portable Stimulus (PSS) and cross-level stimulus reuse \nHands-on experience with protocols (e.g., PCIe, Ethernet, CXL, UCIe) \nDeep understanding of SoC architectures in AI, HPC, or Networking domains \nExperience with multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement \nStrong debugging skills and ability to handle complex system-level issues\nGood to Have\nExperience with AI/ML applications in verification workflows\nExposure to emulation, prototyping, or hybrid verification platforms\nFamiliarity with performance verification and power-aware verification\nKnowledge of industry-standard protocols (e.g., PCIe, Ethernet, CXL, UCIe) \nExperience building verification frameworks reused across multiple tape-outs\n\nKey Attributes\nStrong architectural thinking with a systems-level mindset\nHigh ownership with a quality-first approach\nBias toward automation, reuse, and scalability\nPassion for adopting cutting-edgetechnologies, especially AI-driven verification \nAbility to operate in a fast-paced environment with a fail-fast, learn-fast attitude\nExcellent collaboration and leadership skills \nSuccess in This Role Looks Like\nHigh degree of verification reuse across programs\nAchievement of coverage and quality goals within schedule\nReduction in verification cycle time through automation and AI\nStrong track record of first-time silicon success\nMinimal post-silicon escapes and debug cycles","description_format":"text","description_chars":6905,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["AI Chips & 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