{"id":2570196,"url":"https://alion.io/job/tylsemi-soc-architect-2","title":"SoC Architect","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"B","score":75,"open_postings":20,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":["US"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":157000,"max_usd":309000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":18,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"OpenAI","optional":true}],"status":"live","first_seen_at":"2026-05-08T08:50:52Z","employer_posted_date":"2026-05-08","last_verified_at":"2026-10-15T06:43:08Z","board_verified":true,"closed_at":null,"days_open":159,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":159},"description":"About TylSemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TylSemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe are seeking aSoC Architect to define and drive the architecture of next-generation infrastructure. This role involves end-to-end ownership of system and SoC architecture, fromconcept to silicon, with a strong emphasis onscalability, performance, interconnects, and system-level optimization.\nKey Responsibilities\nDefinesystem architecture for complex SoCs, including IO, compute, interconnect and subsystems \nDrive architecture forscalable and modular designs, including chiplet-based systems (UCIe) \nArchitect high-performance data movement across IO interfaces ( PCIe / UCIe / CXL / UALink / ESUN )\nCollaborate with design and DV teams to ensurearchitectural feasibility and efficient implementation\nDevelopperformance models and simulations tovalidatearchitecture choices \nDrive trade-offs across: Performance, Power, Area and Cost \nWork closely with customers and software teams to align architecture withreal-world workloads\nInfluence long-term roadmap and technology direction \nDefinesystem-level verification and validation strategies\nRequired Qualifications\nBachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field \n18+ years of experience inSoC or system architecture\nProventrack recordof architectingcomplex SoCs for AI, HPC, or Networking \nDeep understanding of: \nSystem-level design and trade-offs \n\nHigh-speed IO protocols (UCIe, PCIe, Ethernet) \n\nData movement and interconnect design \n\nExperience withperformance modeling and architectural simulation\n\nStrong cross-functional collaboration skills \nPreferred Qualifications\nKnowledge ofcoherency protocols (CXL, CHI.)\nExperience withpower/performance optimization at system level\nExposure tosoftware-hardware co-design\nExperience withmemory architectures (DDR, HBM, cache hierarchies) \nFamiliarity withchiplet architectures and advanced packaging (2.5D/3D)\nKey Attributes\nStrong system-level thinking and architectural vision \nAbility to balanceinnovation with practical execution\nHigh ownership and accountability \nStrong communicationand leadership skills \nSuccess Metrics\nScalable and efficient SoC architectures across multiple generations \nAchievement of performance, power, and cost targets \nStrong alignment between architecture and silicon outcomes \nReduced architectural rework through early validation","description_format":"text","description_chars":5434,"description_truncated":false,"requirements":{"experience_years_min":18,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Design & Creative"],"lifecycle":[{"event":"open","at":"2026-10-14T22:44:48Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long 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