{"id":2570204,"url":"https://alion.io/job/tylsemi-staff-engineer-design-verification","title":"Staff Engineer - Design Verification","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":95,"open_postings":14,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":136,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"OpenAI","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-25T15:50:22Z","employer_posted_date":"2026-08-25","last_verified_at":"2026-10-17T12:16:58Z","board_verified":true,"closed_at":null,"days_open":52,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":52},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe are seeking a highly experienced Staff Engineer - Design Verification to lead the design verification of next-generation high-speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in PCIe, CXL, Ethernet, UCIe protocols, and advanced SystemVerilog, UVM methodologies, C and SV skills, driving verification strategy, execution, and innovation across complex projects.\nWhat You’ll Do\nVerification Strategy: Define and implement scalable verification plans for PCIe, CXL, and Ethernet subsystems.\nUVM Testbench Development: Architect layered UVM agents, environments, and reusable components for protocol verification.\nProtocol Expertise: Apply in-depth knowledge of PCIe Gen5/Gen6, CXL 3.x, and Ethernet (200G/400G), UCIe PHY and Adaptor layer standards to ensure compliance and robustness.\nCoverage & Metrics: Drive functional coverage closure, assertion-based verification, and metric-driven sign-off.\nDebug & Analysis: Lead root-cause analysis of complex issues across simulation, emulation, and silicon bring-up.\nCollaboration: Partner with design, architecture, and validation teams to deliver high-quality IP and SoC verification.\nMentorship: Guide junior engineers, fostering best practices in verification methodology and protocol expertise.\nWhat We’re Looking For\n8+ years of experience in Design Verification, with strong exposure to complex SoC/IP verification\nBachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field\nProven experience in defining and deploying verification architectures for high-speed protocols\nStrong expertise in SystemVerilog, UVM, coverage-driven verification, and SVA\nDeep hands-on experience with PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G or similar protocols\nExperience with UCIe PHY/Adapter layer verification is highly desirable\nStrong understanding of SoC architecture, high-speed interfaces, and IP integration\nExcellent debugging, problem-solving, technical leadership, and mentoring skills\nGood to Have\nExperience with AI/ML applications in verification workflows\nExposure to emulation, prototyping, or hybrid verification platforms\nFamiliarity with performance verification and power-aware verification\nKnowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe) \nExperience building verification frameworks reused across multiple tape-outs","description_format":"text","description_chars":5490,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Design & Creative"],"lifecycle":[{"event":"open","at":"2026-10-14T22:44:48Z"}],"visa":[],"liveness":{"score":76,"band":"hot","label":"Hiring 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