{"id":2570206,"url":"https://alion.io/job/tylsemi-staff-engineer-physical-design","title":"Staff Engineer - Physical Design","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":95,"open_postings":14,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":136,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"OpenAI","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-09-04T04:42:58Z","employer_posted_date":"2026-09-04","last_verified_at":"2026-10-18T04:20:04Z","board_verified":true,"closed_at":null,"days_open":44,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":44},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe are looking for a highly skilled Staff Physical Design Engineer to drive end-to-end physical implementation for advanced semiconductor designs acrosscutting-edgetechnology nodes. The ideal candidate will lead block/subsystem-level implementation activities, collaborate cross-functionally with RTL, STA, DFT, and CAD teams, and ensure high-quality tape-outs withstrongfocus on power, performance, and area (PPA). This role requires deepexpertisein physical design methodologies, debugging complex issues, and mentoring junior engineers.\nWhatYou’llDo\nLead full-chip or block-level physical design implementation fromfloorplanningto GDS signoff.\nDrivefloorplanning, power planning, placement, CTS, routing, optimization, and physical verification closure. \nAnalyze andoptimizetiming, congestion, IR drop, EM, and power for advanced technology nodes. \nCollaborate with RTL, DFT, STA, package, and CAD teams to resolve implementation and signoff challenges. \nDevelop and improve physical design flows, automation scripts, andmethodologyenhancements. \nSupport tape-out activities and ensure design signoff quality across all implementation stages. \nMentor junior engineers and contribute to technical reviews and best practices. \nWhatWe’reLooking For\nBachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field. \n8+ years of hands-on experience in ASIC/SOC physical design implementation.\nStrongexpertisein industry-standard EDA tools such as CadenceInnovus, Synopsys ICC2,PrimeTime, andStarRC. \nSolid understanding of timing closure, low-power design techniques, signal integrity, IR/EM analysis, and physical verification. \nExperience working on advanced technology nodes (7nm/5nm/3nm preferred). \nStrong scripting skills inTcl, Perl, or Python for automation and flow enhancement. \nExcellent debugging, problem-solving, communication, and stakeholder collaboration skills. \nGood to Have\nExperience withhierarchical and top-level SOC integration. \nExposure to ML/AI-based design optimization methodologies. \nKnowledge of package-aware implementation and multi-die/chiplet architectures. \nSuccess in This Role Looks Like\nConsistent delivery of high-quality physical design milestones with minimal schedule impact. \nSuccessful closure of timing, power, area, and reliability metrics for complex SOC designs. \nProactive identification and resolution of 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