{"id":2278041,"url":"https://alion.io/job/uitzendbureau-nl-soc-verification-engineer-g","title":"SoC Verification Engineer (G)","company":{"id":702104,"name":"Uitzendbureau.nl","domain":"uitzendbureau.nl","url":"https://alion.io/company/uitzendbureau-nl","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":true,"listed_via":null,"ats_vendor":null,"truth_index":{"grade":"A","score":100,"open_postings":36,"ghost_share":0,"stale_share":0,"repost_share":0.194,"time_to_fill_p50_days":13,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Rijswijk, Netherlands"],"countries":["NL"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":4200,"max":null,"currency":"EUR","period":"month","gross":null,"usd_annual":56304},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bash","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-07T08:19:08Z","employer_posted_date":null,"last_verified_at":"2026-10-07T08:19:08Z","board_verified":false,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":23},"description":"Vacaturebeschrijving Als SoC Verification Engineer werk je concreet aan de verificatie van geavanceerde neuromorfe processors en SoC-designs. Je implementeert en onderhoudt SystemVerilog/UVM-omgevingen, schrijft testsequenties en sluit coverage af om te garanderen dat ontwerpen betrouwbaar functioneren. Je werkt nauw samen met ontwerpteams om simulatie-uitvoer te debuggen, root-causes te achterhalen en fixes te valideren. Daarnaast automatiseer je verificatieflows met scripting en EDA-tools om doorlooptijden en kwaliteit te verbeteren. Dit is een fulltime (40 uur) detavast-positie waarbij je direct bijdraagt aan silicon readiness en productgereedheid. We zoeken iemand die gestructureerd werkt, technisch sterk is in debug en scripting, en impact wil maken in een pragmatisch, technisch gedreven team dat verantwoordelijkheid neemt voor chipkwaliteit.\n Functie-inhoud\n Je ontwikkelt en onderhoudt SystemVerilog/UVM-verificatieomgevingen op zowel module- als SoC-niveau.\nJe schrijft testsequenties, definieert functionele coverage-modellen en werkt naar volledige dekking toe.\nJe debugt simulatie-uitvoer met waveform-tools en werkt samen met ontwerpteams om root-cause issues op te lossen.\nJe automatiseert verificatieflows met Python en shell-scripts en optimaliseert EDA-tools voor snelheid en kwaliteit.\n Functie-eisen\n Minimaal 2 jaar ervaring met ontwikkelen van UVM-gebaseerde verificatieomgevingen en coverage-methodologieën.\nHands-on ervaring met SystemVerilog, UVM en functionele coverage, inclusief debuggen met waveform-analyse.\nBekendheid met gate-level simulatie, UPF voor low-power verificatie en SoC-niveau verificatieflows.\nScriptingvaardigheden in Python, Bash of vergelijkbaar en ervaring met automatiseren van verificatieprocessen.\n Wij bieden\n Een marktconform en competitief salaris, afgestemd op je ervaring en verantwoordelijkheden binnen chip-verificatie.\nDetavast-contract met uitzicht op vaste aanstelling en aanwezige pensioenregeling.\nFlexibele werktijden en werk-op-afstand regeling, met vergoedingen voor woon-werkverkeer en kantoorvoorzieningen zoals fruit en drank.\nEen technisch ervaren en ambitieus team waar je direct invloed hebt op verificatiemethodes en silicon readiness.\nSalarisomschrijving€4200.00 - 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