{"id":2992428,"url":"https://alion.io/job/uniconnect-design-verification-staff","title":"Design Verification-Staff","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"D","score":40,"open_postings":33,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":74000,"max_usd":147000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":12},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C++","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2024-12-16T00:00:00Z","employer_posted_date":"2024-12-16","last_verified_at":"2026-10-23T02:38:28Z","board_verified":true,"closed_at":null,"days_open":676,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":675},"description":"Responsibilities\nYou will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.\nSpecific responsibilities include:\nThe right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results. \nDevelop test plans at block, sub-system, and chip level.\nExecute SoC-based verification at full-chip.\nWrite C-based lib packages and tests.\nArchitect and implement scalable and reusable test benches using SystemVerilog and UVM.\nDevelop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.\nAutomating the test environment for randomized testing and scoreboarding.\nUtilize advanced debugging techniques to identify and resolve design and verification issues.\nPerform root-cause analysis and work with design teams to fix identified issues\nDefine and track functional and code coverage metrics to ensure thorough verification.\nEnsure that verification quality meets or exceeds industry standards and project requirements.\nEdge-based AI inference is preferred. \nRequirements\nRequirements\nRequirements\nWhat you need to have to be successful\nBSEE /MSEE 5-8 years Degree of experience in block, sub-system, and full-chip verification\nShould have delivered multiple chips functioning to Specification.\nIdentify and manage verification deliverables, milestones, and schedules.\nProactively identify potential verification risks and develop mitigation strategies. \nCollaborate with design, architecture, and software teams to understand and verify design intent.\nCommunicate verification progress, issues, and results to stakeholders and management.\nStrong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges\nStrong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.\nC-based verification in an SoC environment is required\nExperience with ARM processor-based designs and low-power design techniques is a plus.\nLanguages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or Makefile\nTechnologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5\nPreferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power","description_format":"text","description_chars":2401,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Blockchain & Crypto"],"lifecycle":[{"event":"open","at":"2026-10-21T10:20:31Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long 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