{"id":2992431,"url":"https://alion.io/job/uniconnect-design-verification","title":"Design Verification","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"D","score":40,"open_postings":33,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, 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part of a team in creating state-of-the-art Secure Low Power SoC ARM-based MCU for the Low-End, Mid-End, and High-end performance MCU product line in a IC Design Environment\nResponsibilities:\nTo develop UVM-based test suite and simulation environment for the verification of standalone IP level and SoC ARM-based system connected with many peripheral digital IPs and Analog IPs.\nCapable of designing and building Verification IP from standard industrial specification\nTo implement test cases from product and standard industrial specification to ensure SoC achieve highest possible coverage, using both constraint-randomized and directed test.\nTo develop test environment and create test cases with UPF inputs for verification of IPs/SoC level in a multiple power domains SoC to ensure they meet all functional features in their respective power domain.\nTo document, compile and correlate all test cases to meet all features in Functional Requirement specification\nTo simulate and debug Gatelevel-Netlist for all corners from back-end team Post layout netlist for all corners to close timing before tape-out.\nCapable of debug and working with IP designer to identify failures and also improve on functional and Code coverage.\nRequirements:\nRequires BSc/MSc or PhD in electrical and electronic or Computer engineering\nRequires 5 years or more of experience in building UVM/OVM/VMM equivalent test suite\nRequires strong understanding of state of the art verification techniques including assertion and metric-driven verification methodology, UVM-based\nVery competent in System Verilog, C++ , C , System C and/or Verilog\nExperience in writing of CPF/UPF to enable multiple power domain verification\nStrong experience in working in Synopsys VCS or Cadence IES, and other formal verification tools\nVerification experience and working knowledge of ARM based CPU Core , SPI, I2C, UART, I2C, USB, PCIe , and/or any other wired protocol with transceivers are strong added advantages\nCapable of leading, review and guiding younger verification engineers in their daily verification tasks\nAble to work in a team with a strong drive to excel\nAble to work independently on a given assignment and work hard to finish on time\nGood written and communication skills\nRequirements\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n5+ years of experience in SoC/ASIC design verification, with hands-on expertise in UVM and SystemVerilog.\nStrong understanding of verification methodologies (UVM/OVM/VMM) and design processes.\nProficiency with simulation tools such as VCS, ModelSim, or Questa.\nExperience with scripting languages (Python/Perl/TCL) for automation in verification workflows.\nSolid debugging and problem-solving skills.\nExcellent communication and teamwork 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