{"id":2907912,"url":"https://alion.io/job/uniconnect-dft-engineer","title":"DFT Engineer","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":12500,"max_usd":27000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":5256},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Synopsys DFTMAX","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2024-08-23T00:00:00Z","employer_posted_date":"2024-08-23","last_verified_at":"2026-10-22T00:32:53Z","board_verified":true,"closed_at":null,"days_open":790,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":789},"description":"Work with front-end team, DFT, and cross-functional teams to provide the solutions and make sure DFT DRCs are fixed \nGenerating high-quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques.\nRequirements\nBE/ BTech/ MTech/MS/ PhD in Electronics, Electrical, Computer Engineering or Computer Science Engineering with 4- 10 years of exp.\nHighly motivated and driven to face challenging design and debug problems \nIn-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis.\nAnalyze the design and propose the best compression technique.\nIn-depth knowledge and hands-on experience in Scan insertion and validation, BIST, LBIST, MBIST insertion and verification, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis, and sign-off.\nHands-on experience in various DFT aspects like Scan insertion, MBIST and Boundary Scan, ATPG, Pattern validation at block level as well as Full-chip level\nTessent DFT expertise - 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