{"id":2907899,"url":"https://alion.io/job/uniconnect-physical-design-engineer","title":"Physical Design Engineer","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"D","score":40,"open_postings":33,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bayan Lepas, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Validator","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-04-08T00:00:00Z","employer_posted_date":"2026-04-08","last_verified_at":"2026-10-26T23:04:50Z","board_verified":true,"closed_at":null,"days_open":202,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":201},"description":"Job Description:\nResponsibilities include (but are not limited to):\nYou will be participating in the leading-edge System-On-a-Chip (SoC) design projects using cutting-\nedge process technology nodes for various client applications.\nExecute complete physical design flow from RTL to GDS (synthesis, floorplan, power grid, place\nand route, clock tree synthesis), participating in design/architecture reviews to track design\nmilestones.\nEvaluate and improve physical design methodologies to handle increasingly complex SoC/IP\ndesigns within aggressive, market-driven schedules.\nActively work as part of a team both locally and with remote or multi-site teams.\nActively assists full chip timing constraints development, full chip Static Timing Analysis, and\ntiming signoff for a complex, multi-clock, multi-voltage SoC.\nActively assists in full chip physical verification activities including DRC and LVS convergence &\nEM/IR convergence\nRequirements\nKey Requirements:\nMinimum of Bachelor’s degree in electrical engineering, Electronics Engineering, Computer\nEngineering, or a related discipline.\nStrong understanding of digital logic, VHDL/RTL representations, and Verilog.\nProficiency in Perl, TCL, and Python for CAD flow automation and optimization.\nExperience with Synopsys EDA tools, including Fusion Compiler, PrimeTime, IC Validator, and VC\nLow-Power.\nSuccessful completion and/or tapeouts on advanced FinFET technology nodes (16nm, 12nm, 7nm,\n5nm, 3nm), including low-power design methodologies\nHands-on experience with place-and-route (PnR) including floorplanning & clock tree synthesis\n(CTS), physical verification, timing convergence and IR drop analysis.\nExperience in automated design flows and automated synthesis.\nAdditional Skills:\nHands-on experience with full-chip or sub-chip Static Timing Analysis, timing constraint\ndevelopment, and timing closure.\nExperience with advanced sign-off activities, including Lint, CDC, LEC, scan, and ECO flows.\nExperience in top-level physical implementation.\nExperience with Cadence EDA tools, including Innovus, Tempus, Virtuoso, and Conformal\nLow-Power.\nExperience with power analysis and power optimization techniques.","description_format":"text","description_chars":2170,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-20T08:32:28Z"}],"visa":[],"liveness":{"score":1,"band":"cold","label":"Long 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