{"id":2907902,"url":"https://alion.io/job/uniconnect-serdes-digital-design-architect","title":"Serdes Digital Design Architect","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"D","score":40,"open_postings":33,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"C","optional":true},{"name":"Embedded C","optional":true}],"status":"live","first_seen_at":"2025-09-23T00:00:00Z","employer_posted_date":"2025-09-23","last_verified_at":"2026-10-24T17:54:12Z","board_verified":true,"closed_at":null,"days_open":396,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":396},"description":"We are looking for a veteran digital architect who can own and drive the digital subsystems of our next-generation 112 Gb/s-and-beyond Ethernet SerDes.\nThis role collaborates closely with analog, DSP, firmware, and SoC teams, translating high-level requirements into clean RTL that meets power, performance, and area (PPA) targets-and also guide the design through synthesis, STA, and physical implementation.\nKey Responsibilities:\n· Define and document the digital micro-architecture for PMA/PMD/PCS blocks, including DSP datapaths and control processors.\n-Write high-quality Verilog RTL, verify it (directed + UVM), and debug corner cases across multiple asynchronous clock domains.\n· Collaborate daily with analog designers to understand and model mixed-signal effects, ensuring robust digital-on-top flows.\n· Craft timing constraints, run STA, and close timing in cutting-edge FinFET nodes.\n· Drive lint/CDC/RDC clean-up and formal checks.\n· Explore FPGA/prototype platforms to validate algorithms and bring-up firmware pre-silicon.\n· Contribute to embedded microcontroller firmware for calibration, adaptation, and link-training routines.\nRequirements\nRequirements:\n· Master's degree or higher in Electrical Engineering\n· 10+ years of hands-on experience architecting and implementing high-speed (>32 Gb/s) SerDes or similar high-performance mixed-signal IPs.\n· Deep expertise in Verilog/SystemVerilog, synthesis, and STA; familiarity with physical design flows (floor-planning, CTS, routing, IR-drop, EM).\n· Proven ability to balance PPA trade-offs and to communicate them clearly to both analog and digital peers.\n· Solid grasp of DSP concepts and algorithms (FFE, DFE, CTLE, FEC).\n· Working knowledge of the Ethernet protocol stack (IEEE 802.3bs/cd/cg) and PMA/PMD/PCS layer requirements.\n· Comfortable with multi-clock-domain design, CDC strategies, and industry-standard verification tools.\n· Self-starter who can triage issues across RTL, gate-level netlists, and lab silicon.\nBonus points for: - FPGA/emulation bring-up experience. - Embedded C/Firmware development for RISC-V or proprietary microcontrollers. - Exposure to advanced process nodes (7 nm, 5 nm, 3 nm)","description_format":"text","description_chars":2177,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-20T08:32:28Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long shot","p_open":1,"p_active":0.138,"p_room":0.28,"age_days":396,"expected_fill_days":31,"reasons":["conf:0","agency","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/uniconnect-serdes-digital-design-architect","json_url":"https://alion.io/job/uniconnect-serdes-digital-design-architect.json","meta":{"generated_at":"2026-10-24T20:02:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":29314,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":258901},"rest":"https://alion.io/mcp/rest/get_company?id=258901"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Funiconnect-serdes-digital-design-architect"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Funiconnect-serdes-digital-design-architect"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Funiconnect-serdes-digital-design-architect"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/uniconnect-serdes-digital-design-architect\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Funiconnect-serdes-digital-design-architect"}]}