{"id":2907908,"url":"https://alion.io/job/uniconnect-sta-engineer","title":"STA Engineer","company":{"id":258901,"name":"Uniconnect","domain":"uniconnect.com.sg","url":"https://alion.io/company/uniconnect","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"D","score":40,"open_postings":33,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":39000,"max_usd":79000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":358},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Tempus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Wi-Fi","optional":false}],"status":"live","first_seen_at":"2024-12-17T00:00:00Z","employer_posted_date":"2024-12-17","last_verified_at":"2026-10-24T05:48:48Z","board_verified":true,"closed_at":null,"days_open":676,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":675},"description":"Job Responsibilities:\nPerformdetailed STA on digital designs used in networking and audio\nsolutions at various stages of the IC design flow (pre-layout,\npost-layout).\n\nIdentify, analyze, andresolve timing violations in critical paths, ensuring low latency and high\nthroughput for networking and audio processing applications.\n\nConduct multi-mode,multi-corner (MMMC) analysis to ensure timing closure under different\noperating conditions, including power-saving modes.\n\nDevelop, validate, andoptimize timing constraints tailored for high-speed networking interfaces\nand high-fidelity audio processing circuits.\n\nDefine and validateclock definitions, I/O constraints, multi-cycle paths, and false paths,\nensuring robust performance in real-world applications.\n\nWork closely with thePhysical Design team to address timing issues, suggest optimizations, and\nsupport clock distribution for complex networking and audio processing\ncircuits.\n\nPerform final timinganalysis and sign-off, ensuring that our ICs meet stringent timing, area,\nand power requirements for networking and audio applications.\n\nWork with post-siliconvalidation teams to correlate timing models with actual silicon\nmeasurements, ensuring that our networking and audio solutions perform as\nexpected in the field.\n\nRequirements\nRequirements:\nBachelor’s or Master’sdegree in Electrical Engineering, Computer Engineering, or a related\nfield.\n\n6+ years of experiencein STA for digital ICs, preferably in the networking or audio\ndomain.\n\nStrong understanding ofdigital design principles, timing concepts, and semiconductor physics.\n\nExperience with timinganalysis for designs at 28nm and below, with a focus on high-speed data\nand signal processing.\n\nProficiencyin STA tools such as Synopsys PrimeTime, Cadence Tempus, or\nsimilar.\n\nSolid understanding ofCMOS technology, standard cell libraries, and PVT variations, with a focus\non high-performance networking and audio applications.\n\nStrong scripting skills(e.g., TCL, Perl, Python) for automation of STA processes.\n\nAbility to work in acollaborative environment, with excellent communication and\nproblem-solving skills.\n\nExperience with timinganalysis for high-speed networking interfaces (e.g., Ethernet, Wi-Fi) or\naudio processing circuits (e.g., DACs, ADCs).\n\nFamiliarity withlow-power design techniques and their impact on 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