{"id":1637651,"url":"https://alion.io/job/upscale-ai-asic-design-principal-engineer","title":"ASIC Design - Principal Engineer","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":250000,"max":265000,"currency":"USD","period":"year","gross":null,"usd_annual":265000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-08-14T00:29:31Z","employer_posted_date":"2026-08-14","last_verified_at":"2026-10-01T21:40:16Z","board_verified":true,"closed_at":null,"days_open":50,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":50},"description":"Job Responsibilities:\nAs a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs. \nResponsible for the logic design/RTL entry that meets the power, performance, area targets. \nCollaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure\nWork closely with the physical design team on timing closure and area optimization \nWork with the design for test team to integrate DFT logic\nWork independently, communicate effectively and collaborate with cross functional teams \nRequirements:\nBE or MS in EE, CE, CS \n5+ years of related technical engineering experience.\n5+ years of industry experience in logic design on complex ASICs\nExperience with SystemVerilog for logic design\nUnderstanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure\nProficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.\nAble to thrive or lead in a fast-paced startup environment.\nPreferred:\n12+ years of relevant industry experience with a proven track record of successful tapeouts \nScripting proficiency using Python, Perl etc. \nExperience with front end design tools like LINT, CDC, RDC\nExposure to silicon bring-up \nAnalyzing timing, area, power reports and ability to drive design fixes \nKnowledge of verification principles and coverage and ability to debug complex test cases\nBasic understanding of formal verification \nPast work experience on high performance, low latency networking ASICs is a big plus \nGrowth mindset and enthusiasm to learn and grow in a fast paced environment","description_format":"text","description_chars":1782,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"liveness":{"score":18,"band":"cold","label":"Long shot","p_open":1,"p_active":0.526,"p_room":0.35,"age_days":49,"expected_fill_days":24,"reasons":["conf:8","win:tail"],"computed_at":"2026-10-02T05:45:00Z"},"pay":{"stated_usd_annual":265000,"is_top_pay":true},"html_url":"https://alion.io/job/upscale-ai-asic-design-principal-engineer","json_url":"https://alion.io/job/upscale-ai-asic-design-principal-engineer.json","meta":{"generated_at":"2026-10-03T00:46:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":497,"day_limit":5000,"remaining_today":4503,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}