{"id":1637661,"url":"https://alion.io/job/upscale-ai-design-verification-engineer","title":"Design Verification Engineer","company":{"id":3854037,"name":"Upscale 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Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-01T22:17:38Z","employer_posted_date":"2026-07-01","last_verified_at":"2026-10-07T00:19:34Z","board_verified":true,"closed_at":null,"days_open":97,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":96},"description":"Job Responsibilities\nDesign, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.\nDevelop comprehensive verification plans and create test cases to ensure complete functional coverage.\nVerify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based verification (ABV), formal verification techniques, and functional coverage methodologies.\nPerform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations to validate design quality and completeness.\nDebug and resolve design and verification issues by collaborating closely with design, architecture, and cross-functional engineering teams.\nDrive the adoption of advanced verification methodologies, automation frameworks, and best practices to improve verification quality and efficiency.\nApply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, coverage optimization, and debug productivity.\nContinuously improve verification processes, infrastructure, and reusable verification IP to accelerate development cycles and enhance design quality and reliability.\nJob Requirements\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of industry experience, or a Master's degree with 7+ years of relevant experience.\nProven experience verifying complex ASIC designs at both block and system levels.\nStrong proficiency with SystemVerilog and the Universal Verification Methodology (UVM).\nExtensive knowledge of ASIC design verification methodologies, verification flows, and industry best practices.\nExperience collaborating with cross-functional teams to deliver ASIC products from architecture through first customer shipment (FCS).\nStrong programming and scripting skills in C, C++, and/or Python.\nExcellent debugging and root-cause analysis skills with the ability to independently resolve complex design and verification issues.\nExperience with verification planning, functional coverage, assertion-based verification (ABV), constrained-random verification, and regression management.\nDomain knowledge of Ethernet, PCIe, and switch fabric architectures is highly desirable.\nFamiliarity with data analytics, AI/ML-assisted verification techniques, or automation tools to improve test generation, regression analysis, coverage closure, and debug productivity is a plus.\nStrong analytical, problem-solving, and communication skills with a passion for solving complex technical challenges.\nSelf-motivated, detail-oriented, and able to work effectively both independently and as part of a collaborative engineering team.","description_format":"text","description_chars":2784,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 35","filings_12m":35,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":222500,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA 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