{"id":3433449,"url":"https://alion.io/job/upscale-ai-distinguished-engineer-serdes-clocking","title":"Distinguished Engineer, SerDes Clocking","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":86,"open_postings":21,"ghost_share":0,"stale_share":0.571,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":313000,"max":353000,"currency":"USD","period":"year","gross":null,"usd_annual":353000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-27T19:48:10Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-11-03T10:26:39Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"About the Role\nWe are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.\nWe are seeking an exceptional technical leader to define the clocking architecture for next-generation SerDes, spanning ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks.\nThis is a senior individual contributor role for a recognized expert in high-speed clocking technology who can drive architectural innovation, lead critical circuit development, and solve some of the most challenging jitter, coupling, and power-efficiency problems in advanced CMOS.\nYou will establish the clocking architecture and design methodology for our next-generation SerDes platform, working across analog, mixed-signal, digital, layout, and system teams to deliver exceptional timing performance in advanced process technologies at 5nm and below.\nResponsibilities:\nClocking Architecture: Define and drive the end-to-end clocking architecture for next-generation SerDes, including PLLs, clock generation, multiphase clocking, clock distribution, and integration with transmitter and receiver subsystems.\nUltra-Low-Jitter PLL Design: Lead the architecture and development of ultra-low-jitter PLLs targeting less than 100 fs RMS integrated jitter in advanced CMOS technologies at 5nm and below, meeting stringent system-level timing and noise requirements.\nPLL Architecture Innovation: Evaluate and develop hybrid, digital, and other advanced PLL architectures, making informed trade-offs among jitter, power, area, tuning range, robustness, and implementation complexity.\nMulti-PLL Coupling Management: Develop architectural and circuit-level solutions to mitigate coupling among multiple PLLs and clock-generation blocks, including supply coupling, substrate noise, electromagnetic interactions, reference spurs, and clock-to-clock interference.\nPower-Efficient Clock Distribution: Define and implement advanced clock distribution architectures, including resonant clocking techniques, to reduce clocking power while maintaining stringent jitter, skew, phase-noise, and timing requirements.\nEM Analysis and Optimization: Use electromagnetic simulation and extraction tools to analyze and optimize inductors, resonant networks, clock distribution structures, coupling paths, and high-frequency interconnects.\nModeling and Verification: Develop SystemVerilog-based behavioral models, verification environments, and architectural models for PLLs and clocking subsystems to enable early system integration, design exploration, and verification of key performance requirements.\nCross-Functional Technical Leadership: Partner with SerDes TX, RX, ADC, digital, AMS layout, package, and silicon validation teams to optimize overall link performance and ensure clocking architecture decisions align with system requirements.\nSilicon Execution and Correlation: Drive design reviews, implementation strategy, silicon characterization, jitter and phase-noise analysis, and simulation-to-silicon correlation.\nQualifications:\nMS or PhD in Electrical Engineering or a related field, with extensive experience in high-performance analog and mixed-signal IC design.\nDemonstrated success designing and delivering ultra-low-jitter PLLs (100 fs-class RMS integrated jitter) in advanced CMOS technologies at 5nm or below.\nDeep expertise in PLL architecture and circuit design, including phase detectors or phase-frequency detectors, charge pumps where applicable, loop filters, oscillators, frequency dividers, and loop dynamics.\nStrong understanding of phase noise, integrated jitter, reference spurs, loop stability, supply-induced jitter, and the impact of clock quality on high-speed SerDes performance.\nProven ability to define clocking architectures and translate stringent system-level jitter requirements into circuit-level specifications and implementation strategies.\nExperience with clock distribution design and the management of coupling, skew, power integrity, and electromagnetic interactions.\nHands-on experience with electromagnetic simulation and extraction tools for analyzing high-frequency circuits and passive structures.\nExperience developing SystemVerilog-based behavioral models and verification environments for PLLs or other mixed-signal clocking systems.\nA strong track record of technical leadership, architectural decision-making, and successful silicon delivery.\nDirect experience developing clocking solutions for 100G+ per-lane SerDes.\nExperience with hybrid PLL architectures, digital PLLs, digitally assisted analog PLLs, or other advanced clock-generation techniques.\nDemonstrated expertise in resonant clock distribution, including resonant network design, energy recovery, clock power optimization, and associated implementation trade-offs.\nExperience managing interference among multiple high-performance PLLs operating within a shared die, including reference distribution, supply isolation, substrate coupling, and electromagnetic coupling.\nProficiency with tools such as Cadence EMX, Ansys HFSS, or equivalent electromagnetic solvers.\nExperience with advanced-node physical implementation, custom layout, parasitic extraction, and silicon debug.\nRecognized technical contributions through successful silicon products, patents, publications, or industry-leading clocking innovations.","description_format":"text","description_chars":5410,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Photo & Video Editing Software","Generative Image"],"lifecycle":[{"event":"open","at":"2026-10-29T01:44:56Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 35","filings_12m":35,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":222500,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, 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