{"id":1637657,"url":"https://alion.io/job/upscale-ai-principal-engineer-design-verification","title":"Principal Engineer – Design Verification","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":436},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-14T07:28:38Z","employer_posted_date":"2026-07-14","last_verified_at":"2026-10-01T21:40:16Z","board_verified":true,"closed_at":null,"days_open":80,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":80},"description":"We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.\nKey Responsibilities\nIP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.\n\nUVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.\n\nTest Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).\n\nAdvanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.\n\nLead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.\n\nCross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.\n\nRequired Qualifications & Skills\nExperience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.\n\nDomain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.\n\nMethodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.\n\nVerification Scope: Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.\n\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\n\nPreferred / Added Advantages\nHands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.\n\nProficiency in Python or Perl for testbench automation and triage scripting.","description_format":"text","description_chars":2441,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"liveness":{"score":16,"band":"cold","label":"Long shot","p_open":1,"p_active":0.463,"p_room":0.35,"age_days":79,"expected_fill_days":24,"reasons":["conf:8","win:tail"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/upscale-ai-principal-engineer-design-verification","json_url":"https://alion.io/job/upscale-ai-principal-engineer-design-verification.json","meta":{"generated_at":"2026-10-03T04:02:08Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4065,"day_limit":5000,"remaining_today":935,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}