{"id":1637660,"url":"https://alion.io/job/upscale-ai-principal-engineer-physical-design","title":"Principal Engineer – Physical Design","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":436},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Machine Learning","optional":true}],"status":"live","first_seen_at":"2026-07-09T16:53:49Z","employer_posted_date":"2026-07-09","last_verified_at":"2026-10-01T21:40:16Z","board_verified":true,"closed_at":null,"days_open":85,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":85},"description":"Role Summary:\nAs a Principal Engineer - Physical Design, you will be responsible for leading the implementation of complex, high-performance ASIC/SoC blocks from RTL to GDSII. You will drive design execution, define physical implementation strategies, and mentor engineers to achieve best-in-class Power, Performance, and Area (PPA) across advanced technology nodes.\nKey Responsibilities:\nOwn end-to-end physical design implementation for large hierarchical blocks, from floorplanning to GDSII signoff.\nDevelop and optimize flows for placement, clock tree synthesis (CTS), routing, and timing closure.\nAnalyze and optimize IR drop, EM, congestion, and power to meet stringent chip targets.\nCollaborate with RTL, DFT, STA, and power teams to resolve cross-domain issues and ensure robust closure.\nDefine and maintain best practices, scripts, and automation flows (Tcl, Python, or Make-based).\nLead timing, physical verification (DRC/LVS), and ECO closure at the block and top level.\nProvide technical leadership for floorplan architecture, partitioning, and clock distribution strategies.\nDrive design convergence on multi-corner multi-mode (MCMM) analysis and ensure signoff consistency.\nPartner with CAD and Foundry teams for technology evaluation, library bring-up, and methodology improvement.\nMentor and guide junior engineers, fostering a strong technical culture within the PD organization.\nRequired Skills & Experience:\n10-15+ years of experience in deep-submicron physical design for complex SoCs or ASICs.\nProven expertise in Cadence Innovus PNR tool.\nStrong understanding of STA (PrimeTime), IR/EM (Voltus), and DRC/LVS (Calibre) flows.\nSolid grasp of RC extraction, clock mesh/tree design, power intent , and hierarchical design methodologies.\nExperience in advanced process nodes (5 nm / 3 nm / N3E/N3P) with exposure to foundry signoff flows. \nExcellent analytical, problem-solving, and debugging skills with attention to detail.\nProficiency in Tcl, Perl, or Python scripting for automation and flow development.\nStrong communication and leadership skills to coordinate across global cross-functional teams.\nPreferred Skills:\nExperience with full-chip integration, floorplan architecture, and package interaction.\nFamiliarity with machine learning or AI-based flow optimization is a plus.\nMasters Degree in Electrical / Electronics / VLSI Engineering preferred.\nKey Traits for Success:\nStrategic thinker with deep technical insight.\nCollaborative mindset and mentoring spirit.\nPassion for continuous learning and process excellence.\nAbility to balance innovation with execution discipline.","description_format":"text","description_chars":2602,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"liveness":{"score":16,"band":"cold","label":"Long shot","p_open":1,"p_active":0.463,"p_room":0.35,"age_days":84,"expected_fill_days":24,"reasons":["conf:8","win:tail"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/upscale-ai-principal-engineer-physical-design","json_url":"https://alion.io/job/upscale-ai-principal-engineer-physical-design.json","meta":{"generated_at":"2026-10-03T03:37:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3597,"day_limit":5000,"remaining_today":1403,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}