{"id":1637665,"url":"https://alion.io/job/upscale-ai-senior-asic-modeling-software-engineer","title":"Senior ASIC Modeling Software Engineer","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":159000,"max":178000,"currency":"USD","period":"year","gross":null,"usd_annual":178000},"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"gRPC","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Protobuf","optional":true}],"status":"live","first_seen_at":"2026-06-16T19:11:57Z","employer_posted_date":"2026-06-16","last_verified_at":"2026-10-01T21:40:16Z","board_verified":true,"closed_at":null,"days_open":108,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":107},"description":"Position Overview\n\nAbout the Role: We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads.\n\nWhat You'll Work On:\n\nASIC Architectural Model: Our current-generation ASIC simulator\n\nNext-gen ASIC models: Future silicon with enhanced AI networking features\n\nMulti-chip simulation: Modeling systems with multiple interconnected ASICs\n\nPerformance optimization: Making large-scale simulations practical\n\nKey Responsibilities\nDesign and implement software model components that accurately simulate ASIC behavior (forwarding engines, schedulers, memory subsystems, control plane interfaces)\n\nTranslate architectural specifications and microarchitecture documents into high-fidelity C++ models, ranging from functionally accurate to performance-accurate depending on the subsystem\n\nDevelop and maintain the register model, memory map, and configuration interfaces\n\nImplement packet processing pipelines for multiple forwarding modes\n\nOptimize model performance for large-scale simulations\n\nCollaborate with RTL engineers to ensure model-to-silicon correlation\n\nWork with the architecture team to validate algorithm and architectural choices through simulation\n\nWork with SDK and platform software teams to enable software development and validation on the model\n\nSupport multiple ASIC versions with maintainable, configurable model architecture\n\nRequirements\n\n7+ years of experience in C/C++ architecture model development, cycle-aware simulation, or ASIC verification\n\nExpert-level C++ programming (modern C++17)\n\nDeep understanding of network switch/router architecture: forwarding tables, scheduling, QoS, ACLs\n\nExperience with packet processing pipelines and dataplane simulation\n\nFamiliarity with hardware description languages (Verilog/SystemVerilog) and reading RTL\n\nExperience with gRPC, Protocol Buffers, or similar IPC mechanisms\n\nExperience with C++ unit testing frameworks (e.g., Google Test)\n\nFamiliarity with Python for test automation, tooling, and scripting\n\nStrong debugging skills across software and hardware domains\n\nNice to Have\n\nExperience with AI/ML networking (scale-up fabrics, RDMA, collective operations)\n\nExperience using ns-3 and/or HTSim to model high performance network architectures.\n\nFamiliarity with SAI (Switch Abstraction Interface) or SONiC\n\nExperience with FPGA prototyping or emulation platforms\n\nBackground in memory subsystem modeling (DDR, HBM, caches)\n\nExperience with configuration-driven simulation frameworks (YAML, JSON, protobuf-based config)","description_format":"text","description_chars":2934,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.343,"p_room":0.28,"age_days":107,"expected_fill_days":24,"reasons":["conf:8","win:tail","crowd:"],"computed_at":"2026-10-02T05:45:00Z"},"pay":{"stated_usd_annual":178000,"is_top_pay":false},"html_url":"https://alion.io/job/upscale-ai-senior-asic-modeling-software-engineer","json_url":"https://alion.io/job/upscale-ai-senior-asic-modeling-software-engineer.json","meta":{"generated_at":"2026-10-03T04:00:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4014,"day_limit":5000,"remaining_today":986,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}