{"id":3123713,"url":"https://alion.io/job/upscale-ai-senior-director-ams-layout-engineering","title":"Senior Director, AMS Layout Engineering","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":86,"open_postings":20,"ghost_share":0,"stale_share":0.55,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"head","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":306000,"max":337000,"currency":"USD","period":"year","gross":null,"usd_annual":337000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-22T19:56:31Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-28T03:52:19Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"About the Role\nWe are building a world-class SerDes engineering team to enable next-generation AI data center connectivity. As Senior Director of AMS Layout Engineering, you will lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation SerDes technologies.\nThis is a strategic technical leadership role for an experienced AMS layout leader who combines deep expertise in advanced-node analog layout, a strong understanding of high-speed PHY design challenges, and a proven track record of building and developing high-performing engineering teams.\nYou will partner closely with analog design, digital design, process technology, and silicon validation teams to translate demanding electrical and physical requirements into robust, high-performance silicon implementations. You will also establish the methodologies, design practices, and organizational capabilities needed to scale our SerDes development efforts.\nResponsibilities:\nTechnical Leadership: Lead AMS layout engineering for advanced high-speed SerDes PHYs, driving physical implementation, optimization, and sign-off across critical analog and mixed-signal circuit blocks.\nAdvanced-Node Expertise: Drive layout solutions at advanced nodes, addressing increasingly complex design rules, restrictive patterning requirements, parasitic effects, device matching, signal integrity, power integrity, and electromigration.\nHigh-Speed PHY Optimization: Partner with circuit designers to optimize layout-sensitive performance, including bandwidth, jitter, noise, matching, power consumption, and overall silicon robustness at 100G+ per-lane data rates.\nPhysical Design Methodology: Establish and improve layout methodologies, design guidelines, verification flows, and quality standards to enable predictable execution and first-silicon success.\nCross-Functional Collaboration: Work closely with AMS design, digital implementation, technology, package, and silicon validation teams to resolve complex integration challenges and deliver competitive silicon.\nOrganization Building: Build and scale a strong AMS layout organization through strategic hiring, technical mentorship, talent development, and succession planning.\nExecution and Delivery: Drive project planning, resource allocation, technical reviews, and execution across multiple concurrent development efforts while maintaining high standards for quality, schedule, and engineering productivity.\nEngineering Excellence: Foster a culture of technical depth, accountability, continuous improvement, and collaboration across geographically distributed teams.\nQualifications:\nBS, MS, or PhD in Electrical Engineering, Microelectronics, or a related field.\nProven experience delivering advanced-node analog or mixed-signal designs at 5nm or below, or equivalent leading-edge process technologies.\nStrong understanding of layout techniques for high-speed SerDes and PHY circuits, including high-speed transmitters, receivers, clocking circuits, PLLs, DLLs, and other timing-critical analog blocks.\nDemonstrated understanding of advanced process design rules, parasitic extraction, physical verification, device matching, signal integrity, and power integrity.\nExperience leading complex silicon development programs from early floorplanning and layout planning through physical verification, tape-out, and silicon bring-up.\nProven ability to recruit, develop, mentor, and retain strong engineering talent while building an effective and collaborative team.\nExcellent communication skills and the ability to influence technical decisions across multidisciplinary engineering organizations.\nPreferred Qualifications:\nDirect experience developing and delivering 100G+ per-lane SerDes PHYs\nExperience leading AMS layout teams for high-speed connectivity products targeting AI accelerators, high-performance computing, networking, or advanced data center applications.\nDeep expertise in layout-sensitive circuit optimization, including parasitic management, coupling and crosstalk mitigation, clock distribution, supply integrity, and electromagnetic interactions.\nExperience with advanced packaging, chiplet integration, and high-bandwidth die-to-die interfaces.\nA strong track record of establishing scalable engineering methodologies and delivering complex, high-performance silicon across multiple technology generations.\nExperience building engineering teams in a fast-paced, high-growth semiconductor organization.","description_format":"text","description_chars":4475,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Photo & Video Editing Software","Generative Image"],"lifecycle":[{"event":"open","at":"2026-10-23T01:26:45Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 35","filings_12m":35,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":222500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":18}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":5,"expected_fill_days":30,"reasons":["conf:2","stale_co","velocity","win:early"],"computed_at":"2026-10-28T05:59:10Z"},"pay":{"stated_usd_annual":337000,"is_top_pay":true},"html_url":"https://alion.io/job/upscale-ai-senior-director-ams-layout-engineering","json_url":"https://alion.io/job/upscale-ai-senior-director-ams-layout-engineering.json","meta":{"generated_at":"2026-10-28T06:23:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8393,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3854037},"rest":"https://alion.io/mcp/rest/get_company?id=3854037"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fupscale-ai-senior-director-ams-layout-engineering"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fupscale-ai-senior-director-ams-layout-engineering"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fupscale-ai-senior-director-ams-layout-engineering"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/upscale-ai-senior-director-ams-layout-engineering\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fupscale-ai-senior-director-ams-layout-engineering"}]}