{"id":3123714,"url":"https://alion.io/job/upscale-ai-senior-director-serdes","title":"Senior Director, SerDes","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":86,"open_postings":21,"ghost_share":0,"stale_share":0.571,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":306000,"max":337000,"currency":"USD","period":"year","gross":null,"usd_annual":337000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-22T19:17:28Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-24T23:10:27Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About the Role\nWe are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.\nWe are seeking an experienced Senior Director of SerDes Engineering to establish, lead, and scale our engineering team across design centers. This is a strategic leadership role combining deep technical expertise in advanced SerDes development with organizational leadership, talent development, and cross-site engineering execution.\nThe successful candidate will build a high-performing team responsible for developing critical SerDes foundation IP and key circuit modules that enable our next-generation connectivity solutions. The team will have meaningful technical ownership, working closely with engineering leadership and design teams across locations to define architectures, develop critical IP, and deliver production-quality silicon.\nWe are particularly interested in leaders with strong experience in high-speed SerDes and foundation IP design who can lead and scale a collaborative, high-performance design center.\nResponsibilities:\nDesign Center Leadership: Establish and lead our SerDes engineering Bangalore design center, including organizational planning, hiring, resource allocation, engineering processes, and long-term capability development.\nTechnical Leadership: Drive the development of advanced SerDes technologies for 100+G-per-lane and next-generation high-speed connectivity, with particular emphasis on receiver and clocking technologies.\nFoundation IP Ownership: Build and lead teams responsible for critical analog and mixed-signal foundation IP, including high-speed circuit building blocks, clocking circuits, receiver components, bandgap, LDO and other reusable technologies.\nCritical Module Development: Establish technical ownership of key SerDes modules, driving architecture, circuit design, implementation, verification, and silicon validation in close collaboration with the global engineering organization.\nTalent Acquisition and Development: Recruit exceptional engineering talent across experience levels, develop technical leaders, establish mentorship programs, and build a sustainable pipeline of future engineering talent.\nEngineering Excellence: Establish rigorous design methodologies, technical review processes, implementation standards, and quality practices to ensure high-quality, predictable silicon delivery.\nCross-Site Collaboration: Build effective working relationships with engineering teams across locations, ensuring seamless technical communication, clear ownership boundaries, efficient decision-making, and alignment on project priorities.\nExecution and Delivery: Own engineering plans, schedules, resource commitments, and technical milestones for the organization, ensuring delivery of critical IP and design modules to support overall product objectives.\nTechnical Culture: Foster a culture of technical depth, accountability, collaboration, and continuous improvement, empowering engineers to take ownership of complex design challenges.\nOrganizational Scaling: Develop a long-term strategy for expanding the design center's technical scope, engineering capacity, and leadership capabilities as the company grows.\nQualifications:\nMS or PhD in Electrical Engineering or a related field.\nExtensive experience in high-speed SerDes or PHY development, with demonstrated technical leadership in complex analog and mixed-signal IC design.\nDirect experience with 100+G SerDes development or closely related next-generation high-speed connectivity technologies.\nStrong understanding of SerDes architecture and implementation, ideally with substantial experience in receiver, clocking, or other critical analog/mixed-signal subsystems.\nProven experience building, managing, and scaling semiconductor engineering teams, including recruiting, mentoring, performance management, and leadership development.\nDemonstrated ability to lead complex silicon development programs from architecture and circuit design through tape-out and silicon validation.\nExperience establishing engineering processes, technical review mechanisms, and organizational practices that support high-quality execution at scale.\nExcellent communication and collaboration skills, with the ability to work effectively across geographically distributed engineering organizations.\nStrong execution skills and the ability to balance technical depth, organizational development, and program delivery.\nPreferred Qualifications\nExperience leading engineering teams responsible for reusable foundation IP and multiple critical analog or mixed-signal design modules.\nExperience establishing or significantly scaling a semiconductor design center.\nA strong track record of recruiting senior engineers and developing technical leaders who can independently own complex design blocks.\nExperience with advanced CMOS process technologies, high-performance analog layout, parasitic extraction, and silicon characterization.\nFamiliarity with advanced packaging, high-bandwidth die-to-die interfaces, and demanding AI data center connectivity requirements.\nExperience managing global engineering teams and coordinating complex development programs across multiple sites.\nDemonstrated success building an engineering organization that delivers meaningful technical innovation and measurable product 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