{"id":3186388,"url":"https://alion.io/job/upscale-ai-senior-distinguished-engineer-serdes-receiver-adc","title":"Senior Distinguished Engineer, SerDes Receiver & ADC","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":86,"open_postings":21,"ghost_share":0,"stale_share":0.571,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":335000,"max":388000,"currency":"USD","period":"year","gross":null,"usd_annual":388000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-22T19:46:47Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-27T23:04:14Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"About the Role\nWe are building a world-class SerDes engineering organization focused on next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.\nWe are seeking an exceptional technical leader to define and drive the architecture and implementation of next-generation SerDes receiver front ends and high-speed analog-to-digital converters (ADCs), targeting ultra-high sampling rates in advanced process technologies at 5nm and below.\nThis is a high-impact technical leadership role for an engineer who combines deep expertise in high-speed analog and mixed-signal circuit design with strong architectural judgment and a proven ability to turn ambitious performance targets into silicon.\nAs a key technical leader, you will shape receiver architecture, drive critical circuit and system-level trade-offs, and work across analog design, DSP, clocking, digital implementation, and silicon validation to deliver industry-leading receiver performance. You will have the opportunity to influence the technical direction of our SerDes platform and establish the foundation for future generations of high-speed connectivity.\nResponsibilities:\nReceiver Architecture: Define and drive the architecture of next-generation, ultra-high-speed SerDes receivers, including the analog front end, ADC, sampling architecture, clocking interfaces, and integration with digital signal processing.\nHigh-Speed ADC Development: Lead the design and optimization of ADCs targeting 100+ GS/s, addressing sampling speed, resolution, linearity, noise, power efficiency, and implementation complexity.\nAnalog Front-End Design: Drive receiver front-end development, including high-bandwidth input stages, equalization, gain control, sampling networks, and other critical analog building blocks.\nAdvanced-Node Implementation: Lead circuit design and implementation in 5nm and below technologies, leveraging advanced CMOS capabilities while managing device limitations, parasitics, variability, power integrity, and layout-dependent effects.\n System-Level Optimization: Establish architectural trade-offs across bandwidth, signal-to-noise ratio, effective number of bits (ENOB), jitter tolerance, power consumption, and DSP complexity to optimize overall link performance.\nClocking and Sampling: Collaborate on clock generation and distribution, sampling-clock quality, aperture jitter, phase noise, and clock-to-data timing requirements at extreme sampling rates.\nTechnical Leadership: Set technical direction, guide critical design decisions, mentor senior engineers, and drive resolution of complex circuit and system-level challenges.\nCross-Functional Collaboration: Partner closely with TX, clocking, DSP, physical design, package, signal integrity, and silicon validation teams to deliver an integrated, high-performance SerDes solution.\nSilicon Execution: Drive feasibility studies, architectural modeling, circuit simulations, design reviews, silicon characterization, and performance correlation to ensure successful implementation and product delivery.\nTechnology Roadmap: Shape the receiver technology roadmap and identify new circuit architectures and implementation techniques to extend the performance and energy-efficiency limits of future SerDes generations.\nQualifications:\nMS or PhD in Electrical Engineering or a related field, with extensive relevant experience in high-speed analog and mixed-signal IC design.\nDemonstrated expertise in high-speed SerDes receiver architecture and circuit implementation, including ADC-based receivers.\nSignificant experience designing advanced CMOS circuits in 5nm or below process technologies.\nStrong hands-on understanding of high-speed ADC architectures and their practical implementation challenges, including sampling networks, comparator design, reference generation, calibration, linearity, noise, and clocking.\nDeep understanding of high-speed receiver performance metrics, including bandwidth, SNR, ENOB, jitter tolerance, equalization, and power efficiency.\nProven ability to make architecture-level decisions informed by circuit-level analysis, system modeling, and silicon measurement.\nTrack record of leading complex, high-performance analog or mixed-signal designs from architecture through tape-out and silicon validation.\nExcellent technical communication skills and the ability to influence design direction across multidisciplinary engineering teams.\nPreferred Qualifications:\nDirect experience with 100G-per-lane or higher SerDes receiver development, including advanced ADC-based architectures.\nExperience developing ADCs with sampling rates approaching or exceeding 100 GS/s, or equivalent expertise in highly time-interleaved, multi-phase, or distributed sampling architectures.\nExpertise in ADC architecture trade-offs, including time interleaving, comparator and sampler design, calibration techniques, mismatch mitigation, and interleaving-spur reduction.\nStrong understanding of the interaction between analog front-end design, clocking, DSP algorithms, and channel characteristics.\nExperience with advanced packaging, chiplet-based systems, and high-bandwidth die-to-die or data center interconnect technologies. Recognized technical contributions through successful silicon products, patents, publications, or leadership in advanced SerDes and ADC development.","description_format":"text","description_chars":5351,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Photo & Video Editing Software","Generative Image"],"lifecycle":[{"event":"open","at":"2026-10-23T23:56:12Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 35","filings_12m":35,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":222500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":4,"expected_fill_days":32,"reasons":["conf:1","stale_co","velocity","win:early"],"computed_at":"2026-10-27T05:46:45Z"},"pay":{"stated_usd_annual":388000,"is_top_pay":true},"html_url":"https://alion.io/job/upscale-ai-senior-distinguished-engineer-serdes-receiver-adc","json_url":"https://alion.io/job/upscale-ai-senior-distinguished-engineer-serdes-receiver-adc.json","meta":{"generated_at":"2026-10-28T00:51:21Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1016,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3854037},"rest":"https://alion.io/mcp/rest/get_company?id=3854037"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fupscale-ai-senior-distinguished-engineer-serdes-receiver-adc"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fupscale-ai-senior-distinguished-engineer-serdes-receiver-adc"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fupscale-ai-senior-distinguished-engineer-serdes-receiver-adc"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/upscale-ai-senior-distinguished-engineer-serdes-receiver-adc\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fupscale-ai-senior-distinguished-engineer-serdes-receiver-adc"}]}