{"id":1637659,"url":"https://alion.io/job/upscale-ai-senior-manager-physical-design","title":"Senior Manager – Physical Design","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"C","score":66,"open_postings":21,"ghost_share":0.571,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":57000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"HPC","optional":true}],"status":"live","first_seen_at":"2026-07-09T16:55:32Z","employer_posted_date":"2026-07-09","last_verified_at":"2026-10-22T06:30:02Z","board_verified":true,"closed_at":null,"days_open":104,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":104},"description":"Role Summary:\n As a Senior Back End Manager - Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.\nThe role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.\nKey Responsibilities:\nLead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.\nOwn overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.\nDrive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.\nProvide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.\nCollaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.\nDrive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.\nEstablish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.\nReview design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.\nLead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.\nPartner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.\nMentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.\nRequired Skills & Experience:\n15-20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.\nProven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.\nDeep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.\nStrong experience with Cadence Innovus based implementation flows.\nExpert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.\nHands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.\nStrong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.\nExperience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.\nStrong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.\nExcellent leadership, communication, decision-making, and cross-functional collaboration skills.\nPreferred Skills:\nExperience leading full-chip implementation and large subsystem ownership.\nExposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.\nExperience building teams, defining organizational processes, and scaling execution methodologies.\nKnowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.\nMaster’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.\nKey Traits for Success:\nStrong technical depth combined with execution leadership.\nOwnership mindset with the ability to drive complex programs to closure.\nAbility to identify risks early and create structured recovery plans.\nPassion for building high-performing teams and mentoring engineers.\nData-driven decision making with focus on quality, predictability, and continuous improvement.\nAbility to balance innovation, schedule pressure, and silicon delivery excellence.","description_format":"text","description_chars":4296,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Photo & Video Editing Software","Generative Image"],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long 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