{"id":1637656,"url":"https://alion.io/job/upscale-ai-senior-principal-engineer-design-verification","title":"Senior Principal Engineer - Design Verification","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":88,"open_postings":20,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":74000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":17,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Shift-Left Security","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-14T07:33:26Z","employer_posted_date":"2026-07-14","last_verified_at":"2026-10-21T14:52:14Z","board_verified":true,"closed_at":null,"days_open":99,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":98},"description":"Experience Level: 17+ Years (or 15+ with exceptional strategic track record)\nLocation: Bangalore, India (On-Site)\nPosition Type: Full-Time\nAbout the Role\nWe are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.\nKey Responsibilities\nSoC Verification Strategy: Define, architect, and govern the overarching verification roadmap and methodology for full-scale, multi-million gate networking SoCs.\n\nMethodology Innovation: Drive the adoption of advanced methodologies. Seamlessly integrate Formal Property Verification (FPV), hardware emulation, and advanced shift-left strategies into the standard SoC timeline.\n\nHigh-Level Governance: Establish, track, and enforce rigorous quality metrics and sign-off criteria across the entire project lifecycle, ensuring zero-defect silicon.\n\nArchitectural Influence: Work directly with Silicon Architects and Design Directors to review specs, optimize micro-architecture for testability/verifiability (DFV), and mitigate risk early.\n\nOrganizational Mentorship: Mentor Principal engineers and technical leads across the site. Champion best practices, drive technical brainstorming, and cultivate a culture of engineering excellence.\n\nCrisis Debugging & Escalation: Act as the ultimate technical authority for critical, complex issues that block project milestones or require deep cross-functional triage.\n\nRequired Qualifications & Skills\nExperience: 15+ to 17+ years of distinguished experience in ASIC/SoC Verification, having successfully guided multiple complex, large-scale tape-outs from concept to production.\n\nDomain Leadership: Deep, comprehensive knowledge of the networking domain, with an understanding of how system-level traffic flow impacts full-chip verification constraints.\n\nFull-Scale SoC Scope: Proven experience leading full SoC-level verification environments, managing top-level testbenches, and coordinating multi-subsystem integration.\n\nExpertise: Authoritative knowledge of System Verilog, UVM, and structural verification planning.\n\nInfluence & Communication: Outstanding executive communication skills. Ability to articulate complex technical risks and trade-offs clearly to both engineering teams and executive management.\n\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\n\nPreferred / Added Advantages\nStrong, proven track record of deploying Formal Verification (FPV) at scale to displace traditional simulation.\n\nExperience integrating hardware emulation (e.g., Palladium, Zebu) into a unified simulation workflow.","description_format":"text","description_chars":3095,"description_truncated":false,"requirements":{"experience_years_min":17,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-01T21:40:16Z"}],"visa":[],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.319,"p_room":0.35,"age_days":98,"expected_fill_days":33,"reasons":["conf:1","stale_co","win:tail"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/upscale-ai-senior-principal-engineer-design-verification","json_url":"https://alion.io/job/upscale-ai-senior-principal-engineer-design-verification.json","meta":{"generated_at":"2026-10-21T18:08:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25610,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3854037},"rest":"https://alion.io/mcp/rest/get_company?id=3854037"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fupscale-ai-senior-principal-engineer-design-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fupscale-ai-senior-principal-engineer-design-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fupscale-ai-senior-principal-engineer-design-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/upscale-ai-senior-principal-engineer-design-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fupscale-ai-senior-principal-engineer-design-verification"}]}