{"id":1637662,"url":"https://alion.io/job/upscale-ai-signal-integrity-senior-engineer","title":"Signal Integrity Senior Engineer","company":{"id":3854037,"name":"Upscale AI","domain":"upscaleai.ai","url":"https://alion.io/company/upscale-ai-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":88,"open_postings":20,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":159000,"max":170000,"currency":"USD","period":"year","gross":null,"usd_annual":170000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"Keysight ADS","optional":false},{"name":"MATLAB","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-06-22T02:42:10Z","employer_posted_date":"2026-06-22","last_verified_at":"2026-10-19T04:19:23Z","board_verified":true,"closed_at":null,"days_open":119,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":119},"description":"Position Summary\n\nWe are seeking an experienced Senior Signal Integrity Engineer to lead SI/PI design and validation activities for next-generation high-speed networking, AI, and data center products. The ideal candidate will have deep expertise in high-speed PCB design, simulation, measurement, and correlation across complex systems operating at 112G and 224G data rates.\nResponsibilities\n- Lead Signal Integrity and Power Integrity analysis for complex PCB and system designs.\n- Define SI/PI architecture, design rules, and channel budgets for high-speed interfaces.\n- Perform detailed channel simulations and optimization using industry-standard tools.\n- Drive correlation between simulation and laboratory measurements.\n- Develop and validate models for packages, PCBs, connectors, cables, and complete channels.\n- Conduct pre-layout and post-layout SI/PI analysis.\n- Perform compliance and interoperability analysis for industry standards.\n- Debug complex signal integrity issues and drive root-cause resolution.\n- Define PCB stackups, routing requirements, via structures, and return path strategies.\n- Mentor junior engineers and provide technical leadership across projects.\n- Collaborate with silicon, package, board, mechanical, and manufacturing teams.\n- Interface with vendors and customers on SI/PI-related technical topics.\nRequired Qualifications:\n\n- BS/MS in Electrical Engineering or related field.\n- 5+ years of experience in Signal Integrity, High-Speed Design, or related areas.\nStrong understanding of:\n\n- Signal Integrity and Power Integrity principles\n- Electromagnetic theory\n- Transmission line analysis\n- High-speed SerDes architectures\n- PCB and package design\n- Channel compliance methodologies\nExtensive hands-on experience with:\n\n- Ansys HFSS\n- Cadence Clarity\n- Cadence Sigrity\n- Keysight ADS\nStrong laboratory experience with:\n\n- Vector Network Analyzer (VNA)\n- TDR/TDT systems\n- High-bandwidth oscilloscopes\n- De-embedding and calibration techniques\n\nExperience analyzing:\n\nPCB channels, Connectors, Cables, Packages, Backplanes and midplanes\nAbility to correlate simulations with measured results and drive design improvements.\nPreferred Qualifications:\n\n- Experience with 112G/224G PAM4 SerDes systems.\n- Experience with Ethernet, PCIe, UCIe, CXL, DDR, or AI networking products.\n- Knowledge of COM, ERL, eye analysis, jitter decomposition, and channel compliance methodologies.\n- Experience with Python, MATLAB, or automation frameworks.\n- Experience leading SI strategy for large-scale hardware programs.\nDesired Attributes:\n\n- Strong technical leadership and mentoring skills.\n- Excellent cross-functional communication.\n- Ability to drive projects independently from concept through production.\n- Customer-facing and vendor collaboration experience.\n- Passion for solving challenging high-speed design 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