{"id":2771905,"url":"https://alion.io/job/ust-associate-iii-vlsi-2","title":"Associate III - VLSI","company":{"id":1774626,"name":"UST","domain":"ust.com","url":"https://alion.io/company/ust-com","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"RippleHire","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, Pakistan"],"countries":["PK"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":72000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":723},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TCL Scripting","optional":false},{"name":"UVM","optional":false},{"name":"Cadence Xcelium","optional":true}],"status":"live","first_seen_at":"2026-10-09T00:00:00Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-17T16:24:56Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Who we are:\nAt UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .\nSummary:\nUST is looking for a Senior SoC/FPGA Verification Engineer with strong expertise in C/C++ based pre-silicon verification, embedded processor validation, and UVM-based verification methodologies.\n\nThe Opportunity:\nWe are seeking an experienced Verification Engineer to drive pre-silicon verification of complex FPGA and SoC platforms. This role requires deep expertise in software-driven verification, embedded processor validation, and verification framework development. The ideal candidate will work closely with architecture, RTL, firmware, and validation teams to ensure robust system functionality and first-pass silicon success.\n\nKey Responsibilities:\nDevelop and execute comprehensive verification strategies for FPGA and SoC designs\nCreate C/C++ based testcases and verification frameworks for embedded processor and subsystem validation\nDevelop and enhance SystemVerilog/UVM testbenches for IP, subsystem, and SoC-level verification\nVerify CPU, memory, DMA, interrupt, boot, and peripheral subsystems across multiple use cases\nDrive coverage-driven verification using constrained-random and directed testing methodologies\nDevelop assertions, checkers, scoreboards, and coverage models to improve verification quality\nDebug complex functional issues across RTL, firmware, and system-level environments\nCollaborate with architecture, design, firmware, and validation teams throughout the development cycle\nDevelop automation and productivity enhancements using Python, Shell, Perl, and Tcl scripting\nParticipate in design reviews, verification sign-offs, and methodology improvements.\n\nRequired Qualifications\nBachelor's or Master's degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related field\n4+ years of experience in FPGA/ASIC Functional Verification\nStrong expertise in C-based or embedded software-driven pre-silicon verification\nHands-on experience in developing C/C++ testcases and verification frameworks for FPGA/SoC verification\nExperience with RISC-V, ARM-based SoCs, or embedded CPU verification\nStrong understanding of FPGA architectures and SoC subsystem design\nGood knowledge of memory architectures, interrupts, DMA, boot flows, and embedded processors\nExperience with SystemVerilog and UVM verification methodologies\nStrong understanding of constrained-random, directed, coverage-driven, and assertion-based verification techniques\nStrong scripting skills in Python, Shell, Perl, and Tcl\nExcellent debugging, analytical, and problem-solving skills\nStrong verbal and written communication skills\n\nPreferred Qualifications\nExperience in end-to-end SoC verification and subsystem integration\nKnowledge of AMBA protocols such as AXI, AHB, and APB\nExperience with simulation tools such as VCS, Xcelium, or Questa\nFamiliarity with firmware-driven verification environments\nExperience in verification automation and regression infrastructure development\nExposure to FPGA prototyping and post-silicon validation is a plus\nExperience leading verification efforts and mentoring junior engineers\n\nLeadership Expectations\nDrive verification strategy and execution for complex FPGA/SoC programs\nChampion software-driven verification methodologies and best practices\nEnsure comprehensive coverage closure and verification sign-off quality\nMentor team members and provide technical guidance across verification activities\nCollaborate effectively across architecture, design, firmware, and validation teams\nIdentify risks early and proactively drive issue resolution to meet project milestones\nWhat we believe:\nWe’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do. \nHumility:\nWe will listen, learn, be empathetic and help selflessly in our interactions with everyone.\nHumanity:\nThrough business, we will better the lives of those less fortunate than ourselves.\nIntegrity:\nWe honour our commitments and act with responsibility in all our relationships.\n\n Equal Employment Opportunity Statement\nUST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.\nAll employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.\nUSTreserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.\n\nTo support and promote the values of UST.\n\nComply with all Company policies and procedures","description_format":"text","description_chars":5415,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams"],"lifecycle":[{"event":"open","at":"2026-10-17T06:35:48Z"}],"visa":[],"liveness":{"score":67,"band":"ok","label":"Likely open","p_open":1,"p_active":0.743,"p_room":0.9,"age_days":8,"expected_fill_days":14,"reasons":["conf:3","win:mid","comp:brand"],"computed_at":"2026-10-17T19:35:53Z"},"pay":null,"html_url":"https://alion.io/job/ust-associate-iii-vlsi-2","json_url":"https://alion.io/job/ust-associate-iii-vlsi-2.json","meta":{"generated_at":"2026-10-17T19:35:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2942,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1774626},"rest":"https://alion.io/mcp/rest/get_company?id=1774626"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fust-associate-iii-vlsi-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fust-associate-iii-vlsi-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fust-associate-iii-vlsi-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ust-associate-iii-vlsi-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fust-associate-iii-vlsi-2"}]}