{"id":2772893,"url":"https://alion.io/job/ust-fpga-design-verification-engineer","title":"FPGA Design Verification Engineer","company":{"id":1774626,"name":"UST","domain":"ust.com","url":"https://alion.io/company/ust-com","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"RippleHire","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":101000,"max":152000,"currency":"USD","period":"year","gross":null,"usd_annual":152000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"VHDL","optional":true}],"status":"live","first_seen_at":"2026-01-22T00:00:00Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-17T16:24:56Z","board_verified":true,"closed_at":null,"days_open":268,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":268},"description":"FPGA Design Verification Engineer\nTechnical Lead II – VLSI\nÂ\nÂ\nWho We Are:\nBorn digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world.\nUST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live.\nWith us, you’ll create a boundless impact that transforms your career-and the lives of people across the world.\nVisit us at UST.com.\n \nYou Are:\nWe are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team, working on state of the art technologies. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. \nÂ\n \nThe opportunity:\n·      Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL).\n·      Write and debug test cases to verify functionality, performance, and corner cases.\n·      Identify and debug issues, working closely with design engineers to resolve them.\n·      Participate in design reviews and contribute to the overall verification strategy.\n·      Stay up-to-date with the latest verification methodologies and tools.\nÂ\nThis position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.\n          Â\nWhat you need: \n·      Strong understanding of FPGA, ASIC, RTL design principles and architectures.\n·      Proficiency in System Verilog and UVM verification methodology.\n·      Experience with Linux operating system.\n·      Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps).\n·      Experience with high-speed I/O design and protocols. Knowledge of PCIe, I2C, SPI, etc.\n··Â      Hands on experience with lab debugging tools including logic analyzer, oscilloscope, and JTAG.\n·      Excellent debugging and problem-solving skills.\n·      Strong communication and collaboration skills.\n·      Desired Skills:\n·      Experience in hardware validation or embedded test automation\n··Â      Experience with scripting languages (e.g., Python, Perl).\n·      Qualification:\n·      Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n·      10+ years of experience in FPGA design or verification.\n·      Familiarity with hardware description languages (e.g., VHDL, Verilog).\n \nÂ\nCompensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.\nRole Location:California\nCompensation Range: $101,000-$152,000\n \n \n \nBenefits\nFull-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits. Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.\nPart-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching.\nFull-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.\nPart-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).\nAll US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.\nÂ\nWhat we believe:\nWe proudly embrace the values that have shaped UST since day one. We build our culture of Humility, Humanity, and Integrity. These values inspire us to nurture a people-first, human centric culture that fosters diversity, prioritizes sustainable solutions, and keeps our people and clients at the forefront of all decisions.\n \nHumility:\nWe will listen, learn, be empathetic and help selflessly in our interactions with everyone.\nHumanity:\nThrough business, we will better the lives of those less fortunate than ourselves.\nIntegrity:\nWe honor our commitments and act with responsibility in all our relationships.\nÂ\nEqual Employment Opportunity Statement \nUST is an Equal Opportunity Employer.\n \nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and “fair chance” ordinances.\nUST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.\n \n \n#UST","description_format":"text","description_chars":6358,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Life insurance","Retirement plans","Vision insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams"],"lifecycle":[{"event":"open","at":"2026-10-17T07:01:09Z"}],"visa":[],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.362,"p_room":0.28,"age_days":268,"expected_fill_days":14,"reasons":["conf:0","win:tail","crowd:brand"],"computed_at":"2026-10-17T17:23:57Z"},"pay":{"stated_usd_annual":152000,"is_top_pay":false},"html_url":"https://alion.io/job/ust-fpga-design-verification-engineer","json_url":"https://alion.io/job/ust-fpga-design-verification-engineer.json","meta":{"generated_at":"2026-10-17T17:23:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":23939,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1774626},"rest":"https://alion.io/mcp/rest/get_company?id=1774626"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fust-fpga-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fust-fpga-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fust-fpga-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ust-fpga-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fust-fpga-design-verification-engineer"}]}