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Salary
≈ $27k – $62k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Staff · 4+ years exp

Confirmed on the employer's own hiring board on Oct 17, 2026. First seen by Alion on Oct 13, 2026.

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UST

UST is a digital transformation and technology services company that partners with clients to deliver AI-driven solutions and business outcomes. It hires data scientists, Salesforce integration specialists, Java, .NET and Node.js developers, mainly in Thiruvananthapuram, Kochi, Bengaluru and Hyderabad. The company is headquartered in Thiruvananthapuram, Kerala, India.

Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .

Job Title: FPGA RTL Design Engineer

Location: Bengaluru, India

Experience: 4+ Years

Role Overview:

We are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.

Key Responsibilities:

  • Design and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications.
  • Perform FPGA synthesis, place & route, timing closure, and performance optimization.
  • Develop and execute functional verification plans, testbenches, and debugging activities.
  • Collaborate with hardware, firmware, and system teams for integration and validation.
  • Analyze and resolve design, timing, and FPGA implementation issues.
  • Support board bring-up, lab validation, and customer issue resolution.
  • Required Skills:

  • 4+ years of experience in FPGA RTL design and verification.
  • Strong proficiency in Verilog/SystemVerilog and digital design fundamentals.
  • Experience with FPGA tools such as Xilinx Vivado, Intel Quartus, or equivalent.
  • Good understanding of timing analysis, CDC, reset synchronization, and FPGA architectures.
  • Experience with simulation and debugging tools (ModelSim, Questa, VCS, etc.).
  • Familiarity with interfaces such as PCIe, Ethernet, DDR, AXI, SPI, I2C, or UART.
  • Strong problem-solving and debugging skills.

    What we believe:

    We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do.

    Humility:

    We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

    Humanity:

    Through business, we will better the lives of those less fortunate than ourselves.

    Integrity:

    We honour our commitments and act with responsibility in all our relationships.

    Equal Employment Opportunity Statement

    UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

    All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

    USTreserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

    • To support and promote the values of UST.

    • Comply with all Company policies and procedures
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