{"id":2772544,"url":"https://alion.io/job/ust-technical-lead-i-vlsi-2","title":"Technical Lead I - VLSI","company":{"id":1774626,"name":"UST","domain":"ust.com","url":"https://alion.io/company/ust-com","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"RippleHire","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-26T00:00:00Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-17T23:02:15Z","board_verified":true,"closed_at":null,"days_open":53,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":53},"description":"Who we are:\nAt UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .\nSummary:\nUST is looking for an RTL Design Lead with experience in PCIe Gen5/6\nThe Opportunity:\n We are looking for a Lead RTL Design Engineer to drive the architecture, design, and execution of high-performance digital subsystems with a strong focus on PCIe-based designs. This role requires deep expertise in RTL development, protocol understanding, and end-to-end ownership from architecture to validation.\nKey Responsibilities:\nOwn end-to-end RTL design and micro-architecture for PCIe-based subsystems\nTranslate system requirements into scalable architecture and RTL implementation\nDesign PCIe datapath, control logic, buffering, flow control, and ordering mechanisms\n• Develop synthesizable RTL using Verilog\n• Lead synthesis, lint, CDC/RDC, timing analysis and closure\n• Drive FPGA/ASIC integration, bring-up, and validation\n• Debug PCIe protocol and system-level issues\n• Collaborate with verification, validation, and firmware teams\n• Lead design reviews, code reviews, and technical sign-offs\nMentor team members and guide technical execution.\n\nRequired Qualifications\n• 8-12 years of RTL design experience (FPGA/ASIC)\n• Strong expertise in Verilog\n• Strong digital design fundamentals (FSMs, FIFOs, pipelines, clock/reset)\n• Deep understanding of PCIe protocol (TLPs, LTSSM, flow control, ordering)\n• Experience with FPGA tools (Vivado/Quartus)\n• Strong experience in synthesis, timing closure, CDC, lint, and debug\n• Strong debugging skills across simulation and hardware\nExperience with high-speed interfaces (PCIe, DDR)\n\nPreferred Qualifications\n• Familiarity with AXI/APB/AHB, I2C, SPI, UART\n• FPGA board bring-up and lab debugging experience\n• Scripting knowledge (Python/Tcl/Shell)\n• Experience with protocol analysis tools\nLeadership Expectations\n• Drive architecture-first design thinking\n• Anticipate PCIe corner cases and design for robustness\n• Improve debug cycle time through better design practices\n• Influence cross-team decisions and technical direction\nWhat we believe:\nWe’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do. \nHumility:\nWe will listen, learn, be empathetic and help selflessly in our interactions with everyone.\nHumanity:\nThrough business, we will better the lives of those less fortunate than ourselves.\nIntegrity:\nWe honour our commitments and act with responsibility in all our relationships.\n\nEqual Employment Opportunity Statement\nUST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.\nAll employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.\nUSTreserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.\n\nTo support and promote the values of UST.\n\nComply with all Company policies and procedures","description_format":"text","description_chars":3831,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams"],"lifecycle":[{"event":"open","at":"2026-10-17T06:49:13Z"}],"visa":[],"liveness":{"score":12,"band":"cold","label":"Long shot","p_open":1,"p_active":0.411,"p_room":0.28,"age_days":53,"expected_fill_days":14,"reasons":["conf:2","win:tail","crowd:brand"],"computed_at":"2026-10-18T01:28:43Z"},"pay":null,"html_url":"https://alion.io/job/ust-technical-lead-i-vlsi-2","json_url":"https://alion.io/job/ust-technical-lead-i-vlsi-2.json","meta":{"generated_at":"2026-10-18T01:28:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2437,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1774626},"rest":"https://alion.io/mcp/rest/get_company?id=1774626"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fust-technical-lead-i-vlsi-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fust-technical-lead-i-vlsi-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fust-technical-lead-i-vlsi-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ust-technical-lead-i-vlsi-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fust-technical-lead-i-vlsi-2"}]}