{"id":2771833,"url":"https://alion.io/job/ust-technical-lead-i-vlsi","title":"Technical Lead I - VLSI","company":{"id":1774626,"name":"UST","domain":"ust.com","url":"https://alion.io/company/ust-com","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"RippleHire","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Siemens ModelSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-13T00:00:00Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-17T19:40:16Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Who we are:\nAt UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .\nJob Title: FPGA RTL Design Engineer\nLocation: Bengaluru, India\nExperience: 4+ Years\nRole Overview:\nWe are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.\nKey Responsibilities:\nDesign and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications.Perform FPGA synthesis, place & route, timing closure, and performance optimization.Develop and execute functional verification plans, testbenches, and debugging activities.Collaborate with hardware, firmware, and system teams for integration and validation.Analyze and resolve design, timing, and FPGA implementation issues.\nSupport board bring-up, lab validation, and customer issue resolution.\nRequired Skills: \n4+ years of experience in FPGA RTL design and verification.Strong proficiency in Verilog/SystemVerilog and digital design fundamentals.Experience with FPGA tools such as Xilinx Vivado, Intel Quartus, or equivalent.Good understanding of timing analysis, CDC, reset synchronization, and FPGA architectures.Experience with simulation and debugging tools (ModelSim, Questa, VCS, etc.).\nFamiliarity with interfaces such as PCIe, Ethernet, DDR, AXI, SPI, I2C, or UART.\nStrong problem-solving and debugging skills.What we believe:\nWe’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do. \nHumility:\nWe will listen, learn, be empathetic and help selflessly in our interactions with everyone.\nHumanity:\nThrough business, we will better the lives of those less fortunate than ourselves.\nIntegrity:\nWe honour our commitments and act with responsibility in all our relationships.\n\n Equal Employment Opportunity Statement\nUST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.\nAll employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.\nUSTreserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.\n\nTo support and promote the values of UST.\n\nComply with all Company policies and procedures","description_format":"text","description_chars":3241,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams"],"lifecycle":[{"event":"open","at":"2026-10-17T06:35:48Z"}],"visa":[],"liveness":{"score":80,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.8,"p_room":1,"age_days":4,"expected_fill_days":14,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-10-17T19:52:42Z"},"pay":null,"html_url":"https://alion.io/job/ust-technical-lead-i-vlsi","json_url":"https://alion.io/job/ust-technical-lead-i-vlsi.json","meta":{"generated_at":"2026-10-17T19:52:42Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3411,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1774626},"rest":"https://alion.io/mcp/rest/get_company?id=1774626"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fust-technical-lead-i-vlsi"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fust-technical-lead-i-vlsi"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fust-technical-lead-i-vlsi"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ust-technical-lead-i-vlsi\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fust-technical-lead-i-vlsi"}]}