{"id":2445551,"url":"https://alion.io/job/vailexa-senior-sram-layout-design-engineer","title":"Senior SRAM Layout Design Engineer","company":{"id":4417762,"name":"VAILEXA","domain":"vailexa.com","url":"https://alion.io/company/vailexa","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Plano, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":124000,"max_usd":226000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1301},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":true}],"status":"live","first_seen_at":"2026-09-22T18:41:07Z","employer_posted_date":"2026-09-22","last_verified_at":"2026-10-15T08:20:43Z","board_verified":true,"closed_at":null,"days_open":22,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":22},"description":"Build More Than Just a Career. Build Your Future.\nAt Vailexa, we’re not just hiring - we’re building thinkers, creators, and future leaders.\nWe believe in giving people the space to grow, the freedom to think, and the opportunity to create real impact from day one. If you’re someone who wants to learn fast, take ownership, and grow beyond limits, you’ll feel right at home here.\nRole Overview We are seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies at the leading edge of process scaling. This is a senior individual-contributor role - you'll own and contribute blocks alongside an established team of leads, not manage one. The role works closely with circuit design, PnR/integration, CAD, and foundry teams to deliver consistent, high-quality memory IP on advanced FinFET/GAA nodes, and includes reviewing layouts and mentoring junior engineers to raise layout quality and execution rigor across the team.\nKey Responsibilities\nManage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.\nDevelop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.\nCarry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.\nSupport EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.\nCollaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.\nCollaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.\nImplement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.\nCollaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.\nReview layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.\nRequired Qualifications\nBSEE or equivalent experience.\n10+ years of hands-on custom IC layout experience as a senior individual contributor (this is not a lead/people-management role), including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.\nHands-on, personal ownership of custom digital SRAM layout - candidates must have directly executed the layout themselves, not simply overseen or reviewed it. This role is not a fit for mixed-signal or analog layout backgrounds.\nHands-on experience at TSMC 3nm or a more advanced process node. Experience limited to 10nm or 7nm does not meet the bar for this role; 5nm is a plus, but 3nm is the minimum.\nSolid grasp of SRAM and memory layout principles.\nExtensive experience in Cadence Virtuoso applied to custom layout creation and assessment.\nExtensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.\nExperience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.\nDirect familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.\nAbility to work effectively with circuit build, physical build, integration, CAD, and foundry teams.\nClear communication, strong ownership, good judgment, and the ability to mentor other engineers.\nPreferred Qualifications\nBackground at TSMC, Intel, Samsung, or Micron (foundries or memory companies with their own advanced process nodes) is strongly preferred - TSMC alumni in particular.\nExperience on TSMC's next-generation, beyond-3nm process nodes.\nKnowledge of, or demonstrated motivation to learn, AI-assisted layout automation tools.\nReady to take the next step?\nIf you’re excited about this role and ready to grow with a team that values ambition, ideas, and impact - we’d love to hear from you.\nApply now and start building your journey with Vailexa.","description_format":"text","description_chars":4406,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-13T13:25:46Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.42,"p_room":0.75,"age_days":22,"expected_fill_days":23,"reasons":["conf:1","agency","velocity","win:late"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/vailexa-senior-sram-layout-design-engineer","json_url":"https://alion.io/job/vailexa-senior-sram-layout-design-engineer.json","meta":{"generated_at":"2026-10-15T10:03:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15161,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4417762},"rest":"https://alion.io/mcp/rest/get_company?id=4417762"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fvailexa-senior-sram-layout-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fvailexa-senior-sram-layout-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fvailexa-senior-sram-layout-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/vailexa-senior-sram-layout-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fvailexa-senior-sram-layout-design-engineer"}]}