{"id":1952401,"url":"https://alion.io/job/verifast-technologies-india-senior-physical-design-engineer","title":"Senior Physical Design Engineer","company":{"id":3800767,"name":"VERIFAST TECHNOLOGIES INDIA","domain":"verifasttech.com","url":"https://alion.io/company/verifast-technologies-india","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ahmedabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":2700000,"max":4200000,"currency":"INR","period":"year","gross":true,"usd_annual":43936},"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-06T10:15:27Z","employer_posted_date":null,"last_verified_at":"2026-10-06T10:15:27Z","board_verified":false,"closed_at":null,"days_open":15,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":15},"description":"Job Title : Senior Physical Design Engineer\n\nLocation : Ahmedabad, Gujarat\n\nCompany : VeriFast Technologies\n\nAbout the Role : \n\nVeriFast Technologies is looking for an experienced Physical Design Engineer with 7+ years of hands-on experience in ASIC/SoC physical implementation and RTL-to-GDS (RT2GDS) flows.\n\nThe ideal candidate should have strong expertise in advanced technology nodes, physical implementation, timing closure, power optimization, and physical signoff. Candidates with 3+ successful tapeouts on advanced nodes such as TSMC 7nm, 5nm, or 3nm will be highly preferred.\n\nKey Responsibilities : \n\n- Own complex ASIC/SoC blocks through the complete RTL-to-GDS physical implementation flow.\n\n- Perform block-level floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.\n\n- Drive timing closure, STA, ECO implementation, power, area, congestion, and routability optimization.\n\n- Perform and drive closure of DRC, LVS, ANT, and other physical verification signoff activities.\n\n- Perform EM/IR (EMIR) analysis and drive issues to closure.\n\n- Analyze implementation challenges and provide RTL and routability feedback to full-chip design stakeholders.\n\n- Identify physical implementation risks proactively and recommend design changes to avoid schedule-critical closure issues.\n\n- Support block integration, hierarchical implementation, and full-chip assembly.\n\n- Collaborate with STA, Power Integrity, DFT, Physical Verification, RTL, Architecture, and Signoff teams.\n\n- Debug and resolve complex timing, congestion, clocking, power, routing, and physical design issues.\n\n- Contribute to improving physical design methodologies, flows, and implementation quality.\n\n- Mentor junior engineers while remaining highly hands-on with physical implementation activities.\n\nRequired Qualifications : \n\n- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.\n\n- 7+ years of hands-on experience in ASIC/SoC Physical Design.\n\n- Strong experience in RTL-to-GDS / RTL-to-GDSII physical implementation flows.\n\n- Hands-on experience with advanced technology nodes, preferably TSMC 7nm / 5nm / 3nm.\n\n- Experience with at least 3 successful tapeouts is highly preferred.\n\nTechnical Skills : \n\n- Floorplanning, Power planning, Synthesis, Placement, CTS, Routing, Physical optimization, ECO implementation, STA, Timing closure, Power and area optimization, Congestion and routability analysis.\n\n- Hands-on experience with DRC, LVS, Antenna (ANT), EMIR, and physical signoff.\n\n- Strong debugging and problem-solving skills.\n\n- Good communication and cross-functional collaboration skills.\n\nPreferred Skills : \n\n- Experience working on complex ASIC/SoC designs and hierarchical implementation.\n\n- Experience with advanced-node physical design challenges.\n\n- Experience working with industry-standard EDA tools from Synopsys, Cadence, or Siemens EDA.\n\n- Experience mentoring engineers and contributing to physical design flow/methodology improvements.\n\nSkills\nPhysical Design, ASIC, SoC, Static Timing Analysis, Floor Planning, RTL, VLSI, DFT, Physical Verification, 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