{"id":3247830,"url":"https://alion.io/job/viasat-senior-design-verification-engineer-space","title":"Senior Design Verification Engineer (Space)","company":{"id":1758272,"name":"Viasat","domain":"viasat.com","url":"https://alion.io/company/viasat-com","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":82,"open_postings":32,"ghost_share":0,"stale_share":0.906,"repost_share":0,"time_to_fill_p50_days":10,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tempe, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":132500,"max":209500,"currency":"USD","period":"year","gross":null,"usd_annual":209500},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":false},{"name":"AI Agents","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"CI/CD","optional":false},{"name":"Copilot","optional":false},{"name":"Jira","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-23T00:21:00Z","employer_posted_date":"2026-10-25","last_verified_at":"2026-10-30T19:37:32Z","board_verified":true,"closed_at":null,"days_open":37,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":37},"description":"About usOne team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.\nWhat you'll do\nAs a senior Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:\nDesign verification planning including test plans\nTestbench development using SystemVerilog/UVM\nHands-on debug with the design team\nEnsuring quality via collection and analysis of coverage metrics including code and functional coverage\nManaging regressions and compute resources\nTool evaluation and license management\nResponsible for owning and driving technical issues to resolution\nYou will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.\nAt Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.\nThis is a site-based role, employees work 3+ days (60%+) per week from a Viasat office or work location within a standard five-day workweek.\nThe day-to-day\nCreate drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs\nMaintaining and communicating program schedule and task tracking (Agile Jira based)\nDebugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers\nRunning and analyzing regressions\nWhat you'll need\nBachelor's Degree in Electrical Engineering, Computer Engineering or a related field\n5+ years Design Verification experience including UVM testbench experience\nFoundational knowledge of digital logic and timing considerations\nAttention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback\nExperience with industry standard simulators such as Questa, Xcelium, and VCS\nProven track record of work in UVM testbench development\nGood oral and written communications skills\nUS citizenship\nAbility to travel up to 10%\nWhat will help you on the job\nStrong written and verbal communication skills, ability to work with a geographically distributed team\nObject oriented programming experience\nFamiliarity with designing and coding for testbench horizontal and vertical re-use\nAbility to work independently, take initiative, and take ownership of tasks and results\nFamiliarity with CI/CD practices\nFamiliarity with AI Agents (Claud Code, Copilot, etc.)\nStrong troubleshooting skills\nSalary range\n$132,500.00 - $209,500.00 / annually.\nFor specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $164,500.00- $246,500.00/ annually\nAt Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.\nEEO Statement\nViasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.\nCreate drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs\nMaintaining and communicating program schedule and task tracking (Agile Jira based)\nDebugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers\nRunning and analyzing regressions\nBachelor's Degree in Electrical Engineering, Computer Engineering or a related field\n5+ years Design Verification experience including UVM testbench experience\nFoundational knowledge of digital logic and timing considerations\nAttention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback\nExperience with industry standard simulators such as Questa, Xcelium, and VCS\nProven track record of work in UVM testbench development\nGood oral and written communications skills\nUS citizenship\nAbility to travel up to 10%","description_format":"text","description_chars":5431,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Satellite Communications","Mobile Networks"],"lifecycle":[{"event":"open","at":"2026-10-25T19:20:14Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 32 · green card filings: 19","filings_12m":32,"filings_prev_12m":42,"green_card_filings_12m":19,"median_offered_wage_usd":142500,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":2}],"liveness":{"score":13,"band":"cold","label":"Long shot","p_open":1,"p_active":0.361,"p_room":0.35,"age_days":37,"expected_fill_days":10,"reasons":["conf:3","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":{"stated_usd_annual":209500,"is_top_pay":true},"html_url":"https://alion.io/job/viasat-senior-design-verification-engineer-space","json_url":"https://alion.io/job/viasat-senior-design-verification-engineer-space.json","meta":{"generated_at":"2026-10-30T21:17:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11656,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1758272},"rest":"https://alion.io/mcp/rest/get_company?id=1758272"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fviasat-senior-design-verification-engineer-space"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fviasat-senior-design-verification-engineer-space"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fviasat-senior-design-verification-engineer-space"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/viasat-senior-design-verification-engineer-space\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fviasat-senior-design-verification-engineer-space"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3247830}},{"tool":"search_jobs","arguments":{"company":"viasat.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3247830},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}