{"id":699950,"url":"https://alion.io/job/voltai-design-verification-engineer","title":"Design Verification Engineer","company":{"id":685840,"name":"Voltai","domain":"voltai.com","url":"https://alion.io/company/voltai","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"D","score":52,"open_postings":30,"ghost_share":0.8,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Palo Alto, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":231000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":568},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"World Models","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2025-11-12T04:05:05Z","employer_posted_date":"2025-11-12","last_verified_at":"2026-10-17T01:23:31Z","board_verified":true,"closed_at":null,"days_open":338,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":338},"description":"About Voltai\nVoltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.\nAbout the Team\nBacked by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.\nAbout this Role\nWe are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. As a Senior Verification Engineer, your role isn’t just verifying chips but redefining how teams verify chips. If you want to build tools that scale with the new era of complexity in hardware, this role offers high ownership and direct impact on real-world chip development.\nWhat You’ll Do\nOwn verification strategy across multiple IP blocks and subsystems, from testbench\n\narchitecture to signoff.\n\nDesign and develop AI assisted workflows that accelerate verification, coverage closure, and debug.\n\nBuild reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling.\n\nCollaborate with ML and software teams to integrate AI models into existing DV environments.\n\nContribute to product direction by exploring how automation can reshape verification methodologies.\n\nWork with customers in a forward deployed capacity when needed, translating real design challenges into product features.\n\nDrive tapeout readiness with full accountability for quality metrics, regression health, and coverage targets.\n\nMentor junior engineers and help define best practices for next generation verification teams.\n\nWhat Makes This Role Unique\nOpportunity to influence the future of tooling and AI guided verification flows.\n\nHigh ownership from day one including technical decisions, roadmap input, and customer interactions.\n\nExposure to both engineering and product thinking.\n\nFast- moving environment built for builders who take initiative rather than wait for direction.\n\nQualifications\n4 to 6 years of hands-on verification experience.\n\nStrong SystemVerilog and UVM skills with proven debug depth.\n\nFamiliarity with Python or similar scripting languages.\n\nCurious mindset toward AI or automation in verification, even if not an expert yet.\n\nAbility to work across domains and communicate clearly with software or ML teams.\n\nComfortable interacting with clients, architects, and leadership when needed.\n\nThrives in a high responsibility environment and enjoys creating solutions that did not exist before.\n\nBonus Skills\nExperience with formal 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