{"id":2640402,"url":"https://alion.io/job/weekday-analog-mixed-signal-engineer","title":"Analog Mixed Signal Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":108,"ghost_share":0,"stale_share":0.972,"repost_share":0,"time_to_fill_p50_days":5,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence AMS Designer","optional":false},{"name":"Cadence Virtuoso","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Python","optional":true},{"name":"TCL Scripting","optional":true}],"status":"live","first_seen_at":"2026-10-15T18:45:56Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-16T01:43:38Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"'\n: - ( - )\nExperience: 8+ yrs\nLocation: Banglore\nWe are looking for an experienced AMS Verification Lead with strong hands-on expertise in Analog/Mixed-Signal (AMS) verification, SystemVerilog, UVM, and Real Number Modeling (RNM). The ideal candidate will lead verification activities for mixed-signal IPs, develop robust verification environments, drive functional coverage closure, and ensure high-quality verification sign-off.\nThis role requires a strong understanding of analog-digital interactions, verification methodologies, simulation workflows, and semiconductor design processes. The successful candidate will combine technical depth with ownership of verification planning, execution, debugging, and team collaboration.\nRequirements\nKey Responsibilities\nLead end-to-end verification of analog and mixed-signal IPs, ensuring functional correctness and verification readiness.\nDevelop comprehensive verification plans, test strategies, testbenches, and verification methodologies based on design specifications.\nBuild, maintain, and enhance SystemVerilog and UVM-based verification environments.\nDevelop, integrate, and validate Real Number Models (RNM) for analog blocks and mixed-signal verification.\nVerify interactions between analog and digital components, including interface behaviour, signal transitions, and functional dependencies.\nPerform functional coverage analysis, identify coverage gaps, debug simulation failures, and drive coverage closure.\nVerify mixed-signal IPs such as ADCs, DACs, PLLs, oscillators, and LDOs.\nManage simulation regressions, track verification schedules, monitor deliverables, and support verification sign-off.\nCollaborate with analog design, digital design, SoC verification, and other engineering teams to resolve technical issues.\nInvestigate verification failures, perform root-cause analysis, and recommend corrective actions.\nMaintain verification documentation, test results, coverage reports, and technical sign-off records.\nIdentify opportunities to improve verification efficiency through automation, reusable components, and better workflows.\nProvide technical leadership, review verification approaches, and mentor engineers on AMS verification best practices.\nWhat Makes You a Great Fit\n8+ years of experience in semiconductor verification, with substantial hands-on experience in Analog/Mixed-Signal verification.\nStrong proficiency in SystemVerilog and UVM for developing and maintaining verification environments.\nPractical experience with Real Number Modeling (RNM) and mixed-signal verification methodologies.\nStrong understanding of analog-digital interface verification and mixed-signal simulation concepts.\nExperience verifying analog or mixed-signal IPs such as ADCs, DACs, PLLs, oscillators, and LDOs.\nProven skills in simulation debugging, functional coverage analysis, regression management, and verification sign-off.\nAbility to independently own verification planning, execution, issue resolution, and technical deliverables.\nFamiliarity with tools such as Cadence Virtuoso, AMS Designer, or equivalent AMS simulation platforms.\nKnowledge of analog behavioural modelling and SystemVerilog-AMS is an advantage.\nExperience with semiconductor IP verification or SoC-level verification is desirable.\nProficiency in Python or Tcl scripting for verification automation is a plus.\nStrong analytical, debugging, and problem-solving skills with excellent attention to detail.\nEffective communication and collaboration skills across multidisciplinary engineering teams.\nPrevious experience mentoring verification engineers or leading technical activities is preferred.","description_format":"text","description_chars":3635,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-15T18:45:56Z"}],"visa":[],"liveness":{"score":52,"band":"ok","label":"Likely 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