{"id":139783,"url":"https://alion.io/job/weekday-asic-rtl-design-engineer-2","title":"ASIC RTL Design Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":91,"ghost_share":0,"stale_share":0.978,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-08T00:00:00Z","employer_posted_date":"2026-08-08","last_verified_at":"2026-10-30T08:04:44Z","board_verified":true,"closed_at":null,"days_open":83,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":83},"description":"'\n: - ( - )\nExperience: 6+ yrs\nLocation: Hyderabad, Telangana, India\nJob Type: Full-time\nWe are looking for experienced ASIC RTL Design professionals to join the semiconductor engineering team at Senior Engineer through Architect levels. This role is suited for highly skilled engineers who have strong expertise in RTL design, digital logic, and ASIC development and are looking to contribute to the architecture and implementation of complex semiconductor products.\nYou will be involved across key stages of the RTL design lifecycle, from understanding architectural specifications and developing microarchitecture to writing synthesizable RTL, supporting verification, and resolving design issues. Depending on your experience level, you may also take ownership of design blocks, provide technical leadership, and contribute to architectural decisions.\nRequirements\nKey Responsibilities\nDevelop high-quality, synthesizable RTL designs based on architectural and microarchitectural specifications.\nTranslate system requirements into efficient digital hardware implementations.\nDesign and implement complex digital logic blocks for ASIC products.\nParticipate in microarchitecture definition, design reviews, and technical discussions.\nDevelop clean, reusable, and scalable RTL using industry-standard design methodologies.\nCollaborate with verification teams to define design requirements and resolve functional issues.\nDebug RTL and simulation issues and work closely with verification teams to identify root causes.\nSupport synthesis, timing analysis, linting, CDC, and other design-quality activities.\nAnalyze and optimize designs for performance, power, area, and reliability.\nWork closely with physical design and implementation teams to address design constraints and integration challenges.\nReview specifications, RTL, design documentation, and technical deliverables for quality and completeness.\nContribute to improving RTL design methodologies, coding standards, and development processes.\nFor senior and architect-level roles, provide technical leadership, mentor engineers, and drive complex design initiatives.\nParticipate in cross-functional technical reviews and contribute to architectural decisions.\nWhat Makes You a Great Fit\n6+ years of hands-on experience in ASIC RTL design or digital hardware development.\nStrong understanding of digital design fundamentals, RTL coding, and ASIC design methodologies.\nProven experience developing synthesizable RTL for complex digital systems.\nStrong proficiency in Verilog/SystemVerilog and RTL design practices.\nExperience with simulation, debugging, linting, CDC, synthesis, and other RTL design-quality processes.\nGood understanding of ASIC development flows and collaboration across design, verification, and physical design teams.\nAbility to analyze complex technical problems and develop efficient, reliable solutions.\nStrong understanding of design trade-offs involving power, performance, and area (PPA).\nExcellent problem-solving, communication, and technical documentation skills.\nAbility to work independently while collaborating effectively with cross-functional engineering teams.\nSenior Engineer candidates should demonstrate ownership of complex RTL blocks, while Architect-level candidates should have strong experience in microarchitecture, technical leadership, and design strategy.\nA strong passion for semiconductor technology and the ability to continuously learn and adapt to evolving ASIC design methodologies.","description_format":"text","description_chars":3491,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-08-08T00:00:00Z"}],"visa":[],"liveness":{"score":2,"band":"cold","label":"Long shot","p_open":1,"p_active":0.081,"p_room":0.28,"age_days":83,"expected_fill_days":6,"reasons":["conf:2","agency","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/weekday-asic-rtl-design-engineer-2","json_url":"https://alion.io/job/weekday-asic-rtl-design-engineer-2.json","meta":{"generated_at":"2026-10-30T09:14:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13248,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":7097},"rest":"https://alion.io/mcp/rest/get_company?id=7097"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fweekday-asic-rtl-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fweekday-asic-rtl-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fweekday-asic-rtl-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/weekday-asic-rtl-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fweekday-asic-rtl-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":139783}},{"tool":"search_jobs","arguments":{"company":"weekday.works","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":139783},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}