{"id":2625156,"url":"https://alion.io/job/weekday-data-verification-998","title":"Data Verification 998","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":108,"ghost_share":0,"stale_share":0.972,"repost_share":0,"time_to_fill_p50_days":5,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-15T14:46:38Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-15T18:45:56Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"'\n: - ( - )\nExperience: 1+ yrs\nLocation: Hyderabad\nWe are looking for a detail-oriented and technically skilled Data Verification Engineer with hands-on knowledge of Verilog and Gate-Level Simulation (GLS) to support digital design verification and validation activities. The ideal candidate will have a strong foundation in digital logic, RTL design concepts, simulation methodologies, and hardware verification workflows.\nThis role is suited for an engineer who is passionate about semiconductor design, functional correctness, and identifying potential issues before hardware implementation. You will work with design and verification teams to validate digital circuits, analyse simulation results, investigate mismatches, and ensure design reliability throughout the development lifecycle.\nRequirements\nKey Responsibilities\nDevelop, execute, and maintain verification test scenarios for digital hardware designs using Verilog-based environments.\nSupport Gate-Level Simulation (GLS) activities using synthesised netlists and appropriate simulation models.\nAnalyse RTL and gate-level simulation results to verify design functionality and identify discrepancies.\nReview design specifications and translate functional requirements into verification scenarios.\nDebug simulation failures by analysing waveforms, signal transitions, timing behaviour, and log files.\nInvestigate mismatches between RTL and gate-level simulation results and coordinate with design teams to identify root causes.\nSupport simulations with timing annotation, including Standard Delay Format (SDF), where applicable.\nIdentify potential timing-related issues, including setup and hold violations, glitches, and unknown signal values.\nWork with verification engineers to improve test coverage, testbench quality, and simulation reliability.\nExecute regression tests and maintain accurate records of test results, failures, and verification status.\nAssist in debugging issues related to reset sequences, clock behaviour, signal connectivity, and logic functionality.\nCollaborate with RTL Design, Physical Design, and Verification teams to resolve design and simulation issues.\nMaintain technical documentation, verification reports, and debugging notes.\nFollow established verification methodologies, coding standards, and project quality processes.\nWhat Makes You a Great Fit\n1+ year of experience in digital design verification, semiconductor engineering, or a related hardware design role.\nStrong foundational knowledge of Verilog HDL and digital logic design.\nFamiliarity with Gate-Level Simulation (GLS) and the simulation of synthesised netlists.\nUnderstanding of RTL design, combinational and sequential logic, clocks, resets, and timing concepts.\nFamiliarity with simulation tools such as Cadence Xcelium, Synopsys VCS, or Siemens Questa is an advantage.\nBasic understanding of SDF annotation, timing checks, and simulation mismatches.\nAbility to analyse simulation logs and waveforms using waveform viewers and debugging tools.\nFamiliarity with Linux environments, command-line tools, and basic scripting is beneficial.\nStrong analytical, debugging, and problem-solving skills with attention to detail.\nGood communication skills and the ability to collaborate effectively with cross-functional engineering teams.\nA bachelor's or master's degree in Electronics Engineering, Electrical Engineering, VLSI, Computer Engineering, or a related discipline is preferred.","description_format":"text","description_chars":3442,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-15T14:46:38Z"}],"visa":[],"liveness":{"score":52,"band":"ok","label":"Likely open","p_open":1,"p_active":0.516,"p_room":1,"age_days":0,"expected_fill_days":5,"reasons":["conf:3","agency","win:early","comp:brand"],"computed_at":"2026-10-15T22:17:25Z"},"pay":null,"html_url":"https://alion.io/job/weekday-data-verification-998","json_url":"https://alion.io/job/weekday-data-verification-998.json","meta":{"generated_at":"2026-10-15T22:17:25Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33798,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":7097},"rest":"https://alion.io/mcp/rest/get_company?id=7097"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fweekday-data-verification-998"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fweekday-data-verification-998"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fweekday-data-verification-998"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/weekday-data-verification-998\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fweekday-data-verification-998"}]}