{"id":1254490,"url":"https://alion.io/job/weekday-design-verification-engineer-3","title":"Design Verification Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":84,"ghost_share":0,"stale_share":0.976,"repost_share":0,"time_to_fill_p50_days":5,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19500,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys HSPICE","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-25T18:46:26Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-29T04:05:08Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"'\n: - ( - )\nExperience: 7+ yrs\nLocation: Hyderabad, Telangana, India\nJob Type: Full-time\nWe are looking for an experienced Senior Full-Chip Verification Engineer to contribute to the development and verification of next-generation NAND Flash Memory technologies. The role combines full-chip verification leadership, SystemVerilog/UVM-based verification, circuit simulation, cross-functional technical collaboration, and AI-assisted engineering.\nThe ideal candidate will have strong expertise in full-chip verification, verification planning, testbench development, SystemVerilog, and UVM, along with the ability to lead multidisciplinary teams and contribute to architectural and verification decisions.\nRequirements\nKey Responsibilities\nContribute to the development of next-generation NAND Flash Memory through verification and optimisation of memory and logic circuits.\nOwn and lead full-chip verification activities, including verification planning, execution, tracking, coverage, and completion criteria.\nDevelop comprehensive verification strategies aligned with product and architectural requirements.\nDesign and maintain scalable SystemVerilog-based testbenches for full-chip verification.\nImplement verification environments using UVM and industry-standard verification methodologies.\nEvaluate key product features and collaborate with multidisciplinary teams to identify technical risks and recommend architectural decisions.\nLead and coordinate verification activities across design, architecture, circuit, layout, and other engineering functions.\nAnalyse verification results, identify failures and coverage gaps, and drive issues through resolution.\nUse circuit simulation tools such as XA, HSPICE, HSim, FineSim, or similar simulators as required.\nDefine verification criteria, methodologies, schedules, milestones, and deliverables for full-chip projects.\nTrack verification progress and communicate risks, dependencies, and status to relevant stakeholders.\nContribute to verification methodology improvements, automation, reusable environments, and engineering best practices.\nLeverage AI-assisted coding and AI tools to automate verification workflows, tools, build processes, and design-analysis activities.\nIdentify opportunities to apply Artificial Intelligence to improve build efficiency, verification productivity, and engineering workflows.\nDrive innovation and continuous improvement across future memory-generation development programs.\nProvide technical leadership and mentoring to verification engineers where required.\nPrepare technical documentation and communicate complex verification concepts clearly to technical and cross-functional stakeholders.\nWhat Makes You a Great Fit\n6-8 years of proven experience in semiconductor verification, with strong experience in full-chip or complex IP verification.\nStrong knowledge of full-chip verification methodologies, planning, execution, coverage, and verification criteria.\nProven hands-on expertise in SystemVerilog and testbench development.\nStrong practical knowledge of UVM and modern verification methodologies.\nBroad understanding of IP verification and semiconductor design verification processes.\nExperience with circuit simulation tools such as XA, HSPICE, HSim, FineSim, or equivalent.\nAbility to lead and coordinate multifunctional engineering teams in a project environment.\nStrong analytical and problem-solving skills with the ability to understand complex technical issues.\nExperience evaluating technical features and contributing to architecture and design decisions.\nDemonstrated ability to use AI-assisted coding, automation, or AI engineering tools to improve development, verification, or analysis efficiency.\nStrong understanding of verification automation and workflow optimisation.\nExcellent written and verbal communication skills, with the ability to explain complex technical concepts to diverse stakeholders.\nStrong interpersonal, collaboration, ownership, and leadership skills.\nExperience working on memory, NAND Flash, or related semiconductor technologies would be an advantage.\nBachelor's, Master's, or Ph.D. degree in Electrical Engineering or a related technical discipline, or equivalent professional experience.","description_format":"text","description_chars":4225,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-25T18:46:26Z"}],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.363,"p_room":0.9,"age_days":2,"expected_fill_days":5,"reasons":["conf:1","agency","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/weekday-design-verification-engineer-3","json_url":"https://alion.io/job/weekday-design-verification-engineer-3.json","meta":{"generated_at":"2026-09-29T04:26:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4205,"day_limit":5000,"remaining_today":795,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}