{"id":1006161,"url":"https://alion.io/job/weekday-design-verification-lead","title":"Design Verification Lead","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":80,"open_postings":117,"ghost_share":0,"stale_share":0.983,"repost_share":0,"time_to_fill_p50_days":5,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-17T16:36:51Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-11-13T01:22:01Z","board_verified":true,"closed_at":null,"days_open":56,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":56},"description":"'\n: - ( - )\nExperience: 7+ yrs\nLocation: Bengaluru\nJob Type: Full-time\nWe are looking for an experienced Senior Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM-based verification to drive verification activities for complex IP and SoC designs.\nThe ideal candidate will have hands-on experience executing multiple IP and SoC verification projects, developing robust verification environments, creating verification plans, debugging functional and gate-level simulations, and driving coverage closure. Experience with at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR is required.\nRequirements\nKey Responsibilities\nDevelop and execute comprehensive design verification strategies and plans for IP and SoC projects.\nTranslate functional and technical requirements into detailed verification plans, test scenarios, and coverage objectives.\nDevelop scalable and reusable SystemVerilog/UVM verification environments.\nBuild UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models.\nSet up, configure, execute, and debug functional and gate-level simulations.\nDevelop and maintain automated regression environments for large verification programs.\nAnalyze simulation failures, identify root causes, and collaborate with RTL and design teams to resolve issues.\nVerify designs using industry-standard protocols such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or equivalent protocols.\nEvaluate, integrate, configure, and validate third-party Verification IP (VIP).\nDevelop effective test strategies for functional, corner-case, error, and protocol-specific scenarios.\nPerform functional and code coverage analysis and drive coverage closure.\nIdentify verification gaps and develop additional tests, assertions, or coverage models where required.\nReview simulation results, regression trends, coverage reports, and verification metrics.\nImprove verification infrastructure, methodologies, automation, and regression efficiency.\nCollaborate with RTL, architecture, firmware, emulation, and other engineering teams throughout the verification lifecycle.\nParticipate in design and verification reviews and contribute technical recommendations.\nMaintain verification documentation, test plans, environments, results, and closure reports.\nMentor junior verification engineers and contribute to verification best practices and methodology improvements.\nWhat Makes You a Great Fit\n7+ years of professional experience in ASIC, SoC, IP, or semiconductor design verification.\nProven experience executing at least 3 IP or SoC verification projects from planning through verification closure.\nStrong hands-on expertise in SystemVerilog and UVM methodology.\nExperience developing and maintaining reusable UVM-based verification environments.\nStrong experience translating functional requirements into verification plans and test strategies.\nHands-on experience setting up and debugging functional and/or gate-level simulations.\nStrong experience developing verification environments and automated regression setups.\nPractical experience with functional coverage, code coverage, coverage analysis, and coverage closure.\nExperience evaluating and integrating third-party VIPs into verification environments.\nStrong understanding of digital design, RTL concepts, simulation, debugging, and verification methodologies.\nHands-on experience with at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR.\nStrong debugging, analytical, and problem-solving capabilities.\nAbility to investigate complex simulation failures and identify root causes across RTL, testbench, and verification environments.\nExperience with industry-standard simulators and verification tools is desirable.\nStrong scripting or automation skills using languages such as Python, Perl, or Tcl are an advantage.\nExcellent communication and collaboration skills with the ability to work effectively across design and verification teams.\nStrong ownership mindset with the ability to independently drive verification activities from planning through coverage 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