{"id":2221704,"url":"https://alion.io/job/weekday-fpga-engineer-chip-design","title":"FPGA Engineer - Chip Design","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":106,"ghost_share":0,"stale_share":0.972,"repost_share":0,"time_to_fill_p50_days":5,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":["IN"],"hiring_countries_total":1,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Cocotb","optional":false},{"name":"OpenROAD Project","optional":false},{"name":"Perl","optional":false},{"name":"Post-training","optional":false},{"name":"Python","optional":false},{"name":"Reinforcement Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilator","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Yosys","optional":false}],"status":"live","first_seen_at":"2026-10-10T14:06:34Z","employer_posted_date":"2026-10-10","last_verified_at":"2026-10-13T08:26:19Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"'\n: - ( - )\nExperience: 3+ yrs\nLocation: Remote (India), India\nJob Type: Full-time\nWe are looking for an experienced ASIC / FPGA Design Engineer with strong hands-on expertise in digital design, RTL development, verification, and implementation flows. The ideal candidate will have practical experience taking chip designs from specifications and RTL through verification, synthesis, physical design, and timing closure.\nThis role combines semiconductor engineering expertise with the development of technical evaluations for AI systems. You will create realistic engineering tasks, develop reference solutions, assess AI-generated designs, and identify functional, timing, and power-performance-area (PPA) issues. The focus is on applying real-world engineering judgement to evaluate how effectively AI agents perform complex chip-design tasks.\nRequirements\nKey Responsibilities\nDevelop realistic engineering evaluation tasks covering RTL design, functional verification, synthesis, physical design, and sign-off.\nWrite reference implementations in Verilog, SystemVerilog, or VHDL, supported by testbenches, constraints, and expected results.\nDefine clear grading criteria and validation methods that reflect industry-standard engineering expectations.\nReview AI-generated RTL, testbenches, hardware designs, and implementation results to identify functional errors and design weaknesses.\nDiagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area decisions.\nEvaluate designs against functional correctness, timing constraints, resource utilisation, and implementation quality.\nConfigure and maintain EDA-based environments that enable AI agents to execute realistic chip-design workflows.\nWork with tools from Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, or Intel Quartus, as relevant to the evaluation.\nDevelop tasks that assess synthesis quality, place-and-route results, static timing analysis, and timing closure.\nIdentify recurring AI-agent failure patterns and convert them into new evaluation scenarios and more challenging engineering tasks.\nCollaborate with engineering and research teams to improve evaluation environments, testing methods, and technical benchmarks.\nAutomate design flows, testing, and result analysis using scripting languages where appropriate.\nDocument reference solutions, design assumptions, failure cases, and evaluation methodologies.\nWhat Makes You a Great Fit\n3-5 years of hands-on ASIC or FPGA design experience, preferably across multiple stages of the digital design flow.\nB.E./B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.\nStrong RTL development skills in Verilog, SystemVerilog, or VHDL.\nPractical experience with design verification, including testbench development, debugging, coverage analysis, and UVM or similar methodologies.\nWorking knowledge of EDA tools and workflows from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.\nUnderstanding of logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure.\nSound engineering judgement when evaluating power, performance, and area (PPA) trade-offs.\nExperience taking at least one project from specification through implementation or tape-out.\nStrong debugging, analytical, and problem-solving skills, with the ability to explain precisely why a design succeeds or fails.\nFamiliarity with Python, Tcl, or Perl for design-flow automation is an advantage.\nExposure to open-source tools such as Yosys, OpenROAD, Verilator, or cocotb is beneficial.\nInterest in AI engineering evaluations, reinforcement-learning environments, or model post-training is a plus, but not required.","description_format":"text","description_chars":3711,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-10T14:06:34Z"}],"visa":[],"liveness":{"score":31,"band":"fade","label":"Fading","p_open":1,"p_active":0.342,"p_room":0.9,"age_days":2,"expected_fill_days":5,"reasons":["conf:0","agency","stale_co","win:mid","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/weekday-fpga-engineer-chip-design","json_url":"https://alion.io/job/weekday-fpga-engineer-chip-design.json","meta":{"generated_at":"2026-10-13T10:01:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15256,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":7097},"rest":"https://alion.io/mcp/rest/get_company?id=7097"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fweekday-fpga-engineer-chip-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fweekday-fpga-engineer-chip-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fweekday-fpga-engineer-chip-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/weekday-fpga-engineer-chip-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fweekday-fpga-engineer-chip-design"}]}