{"id":551672,"url":"https://alion.io/job/weekday-full-chip-sta-signoff-engineer","title":"Full-Chip STA Signoff Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":90,"ghost_share":0,"stale_share":0.978,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":1400000,"max":3200000,"currency":"INR","period":"year","gross":null,"usd_annual":33978},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-09-08T00:00:00Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-10-26T14:11:55Z","board_verified":true,"closed_at":null,"days_open":48,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":48},"description":"This role is for one of Weekday’s clients\nSalary range: Rs 1400000 - Rs 3200000 (ie INR 14 - 32 LPA)\nMin Experience: 6+ years\nLocation: Hyderabad\nJobType: full-time\nWe are looking for an experienced Full-Chip STA Signoff Engineer with 6-17 years of hands-on experience in Static Timing Analysis and timing closure for complex SoC designs. The ideal candidate will have strong expertise in full-chip STA signoff, timing analysis, constraint development, timing closure, and signoff methodologies across advanced semiconductor process nodes.\nYou will work closely with RTL, synthesis, physical design, clock, and implementation teams to analyze timing, identify critical paths, resolve timing violations, and ensure the design meets all timing requirements before tapeout.\nRequirements\nKey Responsibilities\nOwn and execute full-chip Static Timing Analysis (STA) signoff for complex SoC designs.\nPerform timing analysis across multiple modes and corners (MMMC) and ensure complete timing coverage.\nAnalyze setup, hold, recovery, removal, minimum pulse width, clock gating, and other timing checks.\nDevelop, review, and maintain timing constraints including SDC, clocks, generated clocks, input/output delays, false paths, multicycle paths, and clock uncertainty.\nDebug and resolve timing violations across functional and test modes.\nPerform detailed analysis of critical timing paths, identify root causes, and work with implementation teams on timing closure.\nReview timing reports and distinguish between real violations, constraint issues, and tool-related exceptions.\nSupport timing closure through synthesis, place-and-route, ECO, and final signoff stages.\nValidate timing constraints and ensure consistency between RTL, synthesis, STA, and physical implementation environments.\nAnalyze clock skew, latency, reconvergence, clock interactions, and clock-domain timing relationships.\nWork with physical design teams to resolve congestion, buffering, routing, transition, capacitance, and timing-related issues.\nParticipate in timing signoff reviews and provide actionable recommendations for improving PPA and timing.\nPerform timing correlation between different implementation and signoff stages.\nAutomate STA analysis, report generation, and debugging workflows using Tcl, Python, or Perl.\nEnsure timing signoff quality and completeness before tapeout.\nMust-Have Skills\nStrong hands-on expertise in STA Signoff.\n6-17 years of experience in ASIC/SoC physical design or timing analysis.\nProven experience with full-chip timing signoff for complex designs.\nStrong understanding of Static Timing Analysis concepts and methodologies.\nExcellent knowledge of MMMC timing analysis and timing closure.\nStrong expertise in SDC constraints and timing exceptions.\nExperience analyzing setup/hold violations, clock skew, uncertainty, latency, and critical paths.\nHands-on experience with industry-standard STA tools such as Synopsys PrimeTime.\nStrong understanding of clock definitions, generated clocks, asynchronous clocks, false paths, and multicycle paths.\nGood understanding of ASIC implementation, synthesis, place-and-route, CTS, ECOs, and physical effects on timing.\nStrong scripting skills in Tcl and/or Python.\nExperience working with large, hierarchical, multi-million-instance SoC designs.\nGood-to-Have Skills\nExperience with advanced process nodes and complex SoC designs.\nKnowledge of MCMM/OCV, AOCV, POCV, CPPR, and variation-aware timing analysis.\nUnderstanding of SI/crosstalk-aware timing analysis.\nExperience with low-power designs, UPF, and multi-voltage timing analysis.\nExposure to timing ECO implementation and signoff automation.\nFamiliarity with formal equivalence checking and physical verification flows.\nStrong debugging, analytical, and problem-solving abilities.\nEducation\nBachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Microelectronics, or a related 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