{"id":2987849,"url":"https://alion.io/job/weekday-memory-circuit-design-verification-engineer","title":"Memory Circuit Design Verification Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":88,"ghost_share":0,"stale_share":0.977,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Synopsys FineSim","optional":true},{"name":"Synopsys HSPICE","optional":true},{"name":"Synopsys PrimeSim","optional":true}],"status":"live","first_seen_at":"2026-10-21T08:58:12Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-22T18:27:54Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"This role is for one of Weekday’s clients\nMin Experience: 2+ years\nLocation: Hyderabad, Telangana, India\nJobType: full-time\nWe are seeking an experienced Memory Circuit Design Verification Engineer to verify and validate complex memory circuits, memory IP, and full-chip memory designs. The ideal candidate will have a strong understanding of memory architectures, circuit-level simulation, digital verification, and timing analysis, with hands-on experience in pre-silicon verification and debugging.\nIn this role, you will develop and execute verification strategies, perform SPICE/FastSPICE and gate-level simulations, analyze critical memory timing parameters, and validate design robustness across process, voltage, and temperature (PVT) conditions. You will collaborate closely with memory designers, circuit engineers, characterization specialists, and design verification teams to identify design issues, improve verification methodologies, and ensure functional correctness and timing compliance.\nRequirements\nKey Responsibilities\nMemory Circuit Verification: Perform block-level and full-chip verification of memory circuits, memory IP, and associated design components.\nVerification Planning: Develop and execute verification plans, test cases, test vectors, testbenches, and simulation regressions to validate design functionality.\nCircuit Simulation: Run SPICE and FastSPICE simulations to verify circuit behavior, memory operations, and critical timing parameters.\nGate-Level Verification: Execute gate-level simulations with timing delays and analyze logic schematics to identify functional and timing-related issues.\nMemory Timing Analysis: Evaluate read/write operations, setup and hold times, access time, critical data paths, timing margins, and other memory timing characteristics.\nMemory Architecture Validation: Verify memory architectures such as SRAM, DRAM, DDR, LPDDR, and emerging memory technologies based on project requirements.\nDebugging and Root-Cause Analysis: Investigate functional failures, waveform mismatches, timing violations, and circuit-level issues, collaborating with design teams to implement corrective actions.\nPVT and Corner Analysis: Validate design performance and reliability across process corners, voltage variations, temperature conditions, and speed grades.\nVerification Environment Development: Build, maintain, and enhance testbenches, verification environments, automation scripts, and regression frameworks.\nRegression and Coverage Analysis: Analyze simulation results, improve functional coverage, identify verification gaps, and optimize regression efficiency.\nDesign Collaboration: Work with memory circuit designers and cross-functional engineering teams to resolve design issues and improve overall design quality.\nVerification Sign-Off: Support pre-silicon verification sign-off, maintain technical documentation, and communicate verification results and unresolved risks.\nRequired Skills and Qualifications\nHands-on experience in memory circuit design verification, memory IP validation, or related semiconductor verification activities.\nStrong understanding of SRAM and DRAM architectures, memory operation sequences, and fundamental memory timing concepts.\nPractical experience with SPICE and/or FastSPICE circuit simulations.\nUnderstanding of transistor-level and gate-level simulation methodologies.\nProficiency in Verilog and/or SystemVerilog, including testbench development; UVM knowledge is beneficial where applicable.\nStrong knowledge of setup and hold timing, access time, critical paths, timing margins, and waveform analysis.\nUnderstanding of CMOS circuit fundamentals and transistor-level schematics.\nExperience with PVT analysis, process corners, voltage and temperature variations, and design robustness validation.\nStrong debugging, failure analysis, and problem-solving skills.\nFamiliarity with scripting languages such as Python, Perl, Tcl, or Shell for test automation and verification-flow development.\nAbility to collaborate effectively with circuit design, memory design, characterization, and verification teams.\nGood-to-Have Skills\nExperience with custom memory IP verification or full-chip memory circuit validation.\nKnowledge of DDR, LPDDR, and other advanced memory architectures.\nUnderstanding of analog/mixed-signal circuit behavior and CMOS/FinFET technologies.\nExperience with full-chip analog SPICE simulation and timing sign-off.\nFamiliarity with memory compiler verification, memory characterization, and Liberty (.lib) model validation.\nExposure to industry-standard EDA tools such as PrimeSim, FineSim, Spectre, HSPICE, Xcelium, SimVision, or WaveView.\nExperience developing automation frameworks and improving verification workflows.\nStrong documentation, communication, analytical, and cross-functional collaboration skills.","description_format":"text","description_chars":4828,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Electrical & Electronic Engineering"],"lifecycle":[{"event":"open","at":"2026-10-21T08:58:12Z"}],"visa":[],"liveness":{"score":38,"band":"fade","label":"Fading","p_open":1,"p_active":0.379,"p_room":1,"age_days":0,"expected_fill_days":6,"reasons":["conf:3","agency","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/weekday-memory-circuit-design-verification-engineer","json_url":"https://alion.io/job/weekday-memory-circuit-design-verification-engineer.json","meta":{"generated_at":"2026-10-22T18:48:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1709,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":7097},"rest":"https://alion.io/mcp/rest/get_company?id=7097"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fweekday-memory-circuit-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fweekday-memory-circuit-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fweekday-memory-circuit-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/weekday-memory-circuit-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fweekday-memory-circuit-design-verification-engineer"}]}