{"id":3104260,"url":"https://alion.io/job/weekday-physical-design-engineer-3","title":"Physical Design Engineer","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":92,"ghost_share":0,"stale_share":0.978,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"EUV","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"closed","first_seen_at":"2026-10-22T18:27:54Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-27T18:16:18Z","board_verified":false,"closed_at":"2026-10-27T18:16:18Z","days_open":4,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":4},"description":"'\n: - ( - )\nExperience: 8+ yrs\nLocation: Hyderabad, Telangana, India\nAs a Physical Design Engineer, you will drive the creation of high-performance, low-power silicon solutions by translating complex RTL designs into manufacturable, taped-out chips. Leveraging your deep expertise in VLSI layout, you will optimize placement, clock tree synthesis, and routing while ensuring adherence to timing, power, and area constraints. Your role will involve close collaboration with synthesis, verification, and test teams to deliver designs that meet stringent performance and yield targets. You will also mentor junior engineers and contribute to process improvements that enhance productivity and design quality across the development lifecycle.\nRequirements\nLead the physical design flow from floorplanning to tape-out for ASIC and SoC projects.\nPerform rigorous static timing analysis and resolve timing violations using industry tools such as Synopsys IC Compiler and PrimeTime.\nOptimize power consumption through leakage and dynamic power analysis and implement voltage scaling techniques.\nInterface with floorplanning and clock tree synthesis teams to balance area, timing, and power trade-offs.\nConduct detailed layout verification using DRC, LVS, and parasitic extraction tools.\nGenerate and maintain comprehensive design documentation, including mask data and physical design specifications.\nCoordinate with tape-out facilities to ensure correct fabrication data transfer and layout compliance.\nAnalyze and debug manufacturing issues post-tape-out to identify process or design root causes.\nParticipate in design reviews and provide constructive feedback to improve design quality.\nStay updated on the latest VLSI physical design methodologies, tools, and industry best practices.\n8+ years of proven experience in physical design for complex ASIC or SoC projects.\nStrong command of VLSI layout tools, particularly Synopsys IC Compiler, Mentor Calibre, and Cadence Innovus.\nDeep knowledge of static timing analysis techniques using Synopsys PrimeTime or equivalent.\nProficiency in power analysis and optimization, including implementation of power-gating and clock-domain crossing strategies.\nDemonstrated experience with DRC/LVS verification and parasitic extraction workflows.\nExcellent problem-solving skills with a track record of resolving critical timing and layout issues under tight deadlines.\nStrong communication and teamwork abilities, capable of collaborating across multi-disciplinary engineering teams.\nFamiliarity with EUV and 14nm/7nm process design kits and related manufacturing constraints.\nAbility to mentor junior engineers and contribute to process enhancement initiatives.\nHolds a Bachelor’s or Master’s degree in Electrical Engineering, VLSI Design, or a related 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