{"id":3026147,"url":"https://alion.io/job/weekday-principal-engineer-verification","title":"Principal Engineer - Verification","company":{"id":7097,"name":"Weekday","domain":"weekday.works","url":"https://alion.io/company/weekday","size_band":"51-200","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Workable","truth_index":{"grade":"B","score":81,"open_postings":88,"ghost_share":0,"stale_share":0.977,"repost_share":0,"time_to_fill_p50_days":6,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":56000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"closed","first_seen_at":"2026-10-21T19:07:42Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-23T19:34:51Z","board_verified":false,"closed_at":"2026-10-23T19:34:51Z","days_open":2,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":2},"description":"'\n: - ( - )\nExperience: 10+ yrs\nLocation: Bengaluru\nWe are seeking an experienced SoC Verification Technical Lead to lead full-chip System-on-Chip (SoC) verification and drive technical delivery across multiple verification projects or customer engagements. The ideal candidate will have strong expertise in pre-silicon verification, a proven track record of successful SoC tapeouts, and the ability to guide engineering teams toward high-quality verification sign-off.\nThis role requires a combination of deep technical knowledge, verification methodology development, customer engagement, and engineering leadership to ensure functional correctness, coverage completeness, and predictable project delivery.\nRequirements\nKey Responsibilities\nOwn full-chip SoC verification from test-plan development and execution to coverage closure and final sign-off.\nVerify critical SoC functionality, including boot flows, interconnects, memory subsystems, coherency, interrupts, and clock and reset sequencing.\nLead multiple verification projects or a major customer account, ensuring technical quality, schedule adherence, and delivery commitments.\nProvide technical leadership to 6-10 engineers through sub-leads, ensuring effective task allocation, technical guidance, and issue resolution.\nDefine and standardise reusable verification methodologies, including testbench templates, Verification IP (VIP) strategies, regression infrastructure, and coverage workflows.\nDetermine the appropriate distribution of verification activities across simulation, formal verification, emulation, and FPGA prototyping, coordinating with specialist teams.\nEstablish and enforce sign-off criteria for functional coverage, code coverage, toggle coverage, assertions, and Gate-Level Simulation (GLS).\nLead technical reviews, customer discussions, and escalations, communicating verification status, risks, and mitigation plans.\nSupport post-silicon debugging by reproducing silicon issues in pre-silicon verification environments and identifying root causes.\nContribute to effort estimation, project scoping, technical proposals, and Statements of Work (SOW).\nMentor engineers and sub-leads, develop technical training materials, and participate in technical interviews.\nImprove verification productivity through automation, regression optimisation, reusable components, and AI-assisted verification flows.\nWhat Makes You a Great Fit\n10-11 years of experience in semiconductor design verification, with strong expertise in full-chip SoC verification.\nAt least three successful tapeouts, including a minimum of one full-chip SoC tapeout.\nProven technical leadership experience managing or guiding teams of six or more engineers.\nStrong understanding of SoC architecture, verification planning, testbench development, coverage closure, and sign-off processes.\nExperience verifying boot flows, interconnects, memory subsystems, coherency, interrupts, and clock/reset sequencing.\nExpertise in reusable verification methodologies, VIP integration, regression management, and coverage analysis.\nUnderstanding of simulation, formal verification, emulation, FPGA prototyping, and GLS workflows.\nAbility to define verification quality gates, assess technical risks, and drive closure of complex verification issues.\nStrong customer-facing communication, technical presentation, and stakeholder management skills.\nExperience with project estimation, scope definition, technical mentoring, and cross-functional collaboration.\nA continuous-improvement mindset, with interest in automation and AI-assisted verification to improve efficiency and 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