Formal Verification Engineer

This role is for one of the Weekday's clients

Salary range: Rs 500000 - Rs 2200000 (ie INR 5- 22 LPA)

Min Experience: 3+ years

Location: Bengaluru, Karnataka, India

JobType: full-time

We are looking for a skilled Formal Verification Engineer to join our SoC verification team and ensure the correctness, robustness, and reliability of complex digital hardware designs using advanced formal verification methodologies. In this role, you will collaborate closely with RTL designers, design verification engineers, and architects to validate critical SoC components throughout the development lifecycle. If you have strong expertise in formal verification, CDC/RDC analysis, and SystemVerilog Assertions, this is an excellent opportunity to contribute to cutting-edge semiconductor products.

Requirements

Key Responsibilities

• Develop, maintain, and execute formal property checks, including assertions, assumptions, and coverage, for complex SoC components such as interconnects, memory subsystems, power management, and security IPs.
• Perform block-level and chip-level formal verification using industry-standard formal verification tools.
• Collaborate with RTL and design verification teams to debug counterexamples, resolve design issues, and achieve formal verification closure.
• Define and enhance formal verification methodologies, reusable verification frameworks, and best practices across projects.
• Contribute to verification planning, coverage analysis, closure tracking, and tape-out sign-off activities.
• Identify RTL design bugs through formal analysis and provide effective root-cause analysis.
• Drive the adoption of Formal Property Verification (FPV), Sequential Equivalence Checking (SEC), connectivity verification, and other advanced verification techniques.
• Own Clock Domain Crossing (CDC) verification by identifying synchronization issues, validating multi-bit crossings, and ensuring safe clock domain interactions.
• Own Reset Domain Crossing (RDC) verification by validating reset synchronization, deassertion sequencing, and eliminating reset-related functional issues.
• Perform structural and formal CDC analysis to verify synchronizer implementation, reconvergence, asynchronous FIFOs, handshake protocols, and Gray-code based crossings.
• Conduct RDC analysis to verify proper reset synchronization, glitch-free reset deassertion, reset sequencing, and reset domain isolation.
• Use industry-standard CDC/RDC verification tools to perform automated analysis, document waivers where required, and drive closure before tape-out.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.
• 3-8 years of hands-on experience in formal verification of digital hardware or SoC designs.
• Strong expertise in Formal Verification, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) verification.
• Proficiency in SystemVerilog Assertions (SVA) and formal property specification methodologies.
• Hands-on experience with commercial formal verification tools such as JasperGold, VC Formal, Questa Formal, or similar solutions.
• Strong understanding of RTL design, digital logic, SoC architecture, and standard bus protocols such as AXI, AHB, and APB.
• Experience debugging formal verification failures and analyzing counterexamples effectively.
• Excellent analytical, debugging, and problem-solving skills.
• Strong communication skills with the ability to collaborate across cross-functional engineering teams.

Preferred Qualifications

• Experience with Lint analysis and static design verification methodologies.
• Exposure to UPF (Unified Power Format) and low-power verification techniques.
• Familiarity with formal verification methodologies for low-power and power-aware designs.
• Knowledge of verification automation using scripting languages such as Python, Perl, or Shell.
• Experience participating in complete SoC verification and tape-out cycles.