{"id":3670221,"url":"https://alion.io/job/wipro-emulation-architect","title":"Emulation Architect","company":{"id":224,"name":"Wipro","domain":"wipro.com","url":"https://alion.io/company/wipro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Siemens Veloce","optional":true}],"status":"live","first_seen_at":"2026-11-03T09:01:16Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-04T07:29:59Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.Job Description\nRole Purpose\nThe purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction.\nEmulation Architect\nEmulation Architect (ZeBu / HAPS)\n\nExperience\n\n15+ years\n\nLocation\n\nBangalore, Hyderabad, Kochi, Chennai, Pune\n\nDomain\n\nASIC / SoC - Turnkey Silicon\n\nEmployment\n\nFull-time\n\nThe Role\nDefine emulation and FPGA-prototyping strategy for complex SoCs, owning design partitioning, platform bring-up and pre-silicon validation predominantly on Synopsys ZeBu and HAPS.\nWhat You Will Do\nDefine emulation and prototyping strategy: platform selection (ZeBu / HAPS), capacity planning and milestones.\nOwn design partitioning, multi-FPGA / multi-board mapping, clocking, timing and interconnect for emulation targets.\nDrive ZeBu and HAPS compile flows, bring-up, runtime performance and debug visibility.\nBuild transactor, co-emulation and virtual-platform environments for firmware, OS and system-level validation.\nRun hardware/software co-validation, power and performance analysis, and regression automation on emulators.\nPartner with RTL, DV, DFT and SW teams; mentor emulation engineers and lead customer technical reviews.\nWhat You Bring\n15+ years in ASIC/SoC pre-silicon validation, with 8+ years of hands-on ZeBu and HAPS emulation / prototyping.\nProven delivery of multiple SoC emulation or prototyping programs, from compile through system bring-up.\nExpert in design partitioning, FPGA-friendly RTL, clock and memory mapping, and emulation timing closure.\nStrong with AMBA (AXI/AHB/APB), PCIe, Ethernet, USB and DDR/LPDDR subsystems and their emulation models.\nExperience with ARM- or RISC-V-based SoC bring-up, firmware integration and OS boot on emulators.\nScripting and automation in Python, Tcl or Perl; ability to debug at waveform, trace and system level.\nGood to Have\nPalladium or Veloce exposure\nHybrid emulation, virtual platforms and transaction-level co-simulation\nPost-silicon bring-up and chiplet / multi-die validation\nE͏mulation Architect\nEmulation Architect (ZeBu / HAPS)\n\nExperience\n\n15+ years\n\nLocation\n\nBangalore, Hyderabad, Kochi, Chennai, Pune\n\nDomain\n\nASIC / SoC - Turnkey Silicon\n\nEmployment\n\nFull-time\n\nThe Role\nDefine emulation and FPGA-prototyping strategy for complex SoCs, owning design partitioning, platform bring-up and pre-silicon validation predominantly on Synopsys ZeBu and HAPS.\nWhat You Will Do\nDefine emulation and prototyping strategy: platform selection (ZeBu / HAPS), capacity planning and milestones.\nOwn design partitioning, multi-FPGA / multi-board mapping, clocking, timing and interconnect for emulation targets.\nDrive ZeBu and HAPS compile flows, bring-up, runtime performance and debug visibility.\nBuild transactor, co-emulation and virtual-platform environments for firmware, OS and system-level validation.\nRun hardware/software co-validation, power and performance analysis, and regression automation on emulators.\nPartner with RTL, DV, DFT and SW teams; mentor emulation engineers and lead customer technical reviews.\nWhat You Bring\n15+ years in ASIC/SoC pre-silicon validation, with 8+ years of hands-on ZeBu and HAPS emulation / prototyping.\nProven delivery of multiple SoC emulation or prototyping programs, from compile through system bring-up.\nExpert in design partitioning, FPGA-friendly RTL, clock and memory mapping, and emulation timing closure.\nStrong with AMBA (AXI/AHB/APB), PCIe, Ethernet, USB and DDR/LPDDR subsystems and their emulation models.\nExperience with ARM- or RISC-V-based SoC bring-up, firmware integration and OS boot on emulators.\nScripting and automation in Python, Tcl or Perl; ability to debug at waveform, trace and system level.\nGood to Have\nPalladium or Veloce exposure\nHybrid emulation, virtual platforms and transaction-level co-simulation\nPost-silicon bring-up and chiplet / multi-die validation\n͏\nDeliver\n\nNo.\nPerformance Parameter\nMeasure\n\n1.\nProduct design, engineering and implementation\nCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards\n\n2.\nCapability development\n% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs)\n\n͏\nMandatory Skills: ASIC Design.Experience: >10 YEARS\n.Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. 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