{"id":553863,"url":"https://alion.io/job/xanadu-ai-layout-design-engineer-snspds","title":"Layout & Design Engineer - SNSPDs","company":{"id":698,"name":"Xanadu","domain":"xanadu.ai","url":"https://alion.io/company/xanadu-ai","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"HiBob","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":60000,"max":150000,"currency":"CAD","period":"year","gross":null,"usd_annual":105369},"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Photolithography","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-08T18:25:20Z","employer_posted_date":null,"last_verified_at":"2026-09-08T18:25:20Z","board_verified":false,"closed_at":null,"days_open":52,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":52},"description":"Job Description\nJob Title: Layout and Design Engineer - SNSPDs (Superconducting Nanowire Single Photon Detectors). Location: Toronto, Canada\nResponsibilities:\nJoin the Low Temperature Devices team to develop superconducting single-photon detector components that are critical to fault-tolerant quantum computing architecture.\nDevelop the internal PDK with a focus on complex multiplexed multi-pixel detector arrays.\nCapture device layout requirements by collaborating closely with low-temperature device scientists.\nDesign and execute GDS mask layouts for test structures and production tape-outs;\nLead mask design for fabrication process optimization.\nDesign advanced test structures and production tape-outs to bridge simulation and experimental results.\nPerform device-level simulations and develop automated pipelines connecting design environments with simulation tools.\nCollaborate with the Fabrication Engineering team to align design strategies with fabrication capabilities and constraints;\nDrive improvements in key SNSPD performance metrics through layout optimization and innovative design strategies.\nContribute to other simulation or computational projects aligned with the successful candidate's expertise.\nQualifications:\nMSc or PhD in Engineering, Science, or a related field, with 2+ years of industrial experience.\nExpert-level experience with scripted photonic mask design and layout using tools such as gdsfactory, ipkiss3, Virtuoso, OptoDesigner, or similar.\nExpert-level knowledge of physical verification using custom or foundry-provided code, including DRC and LVS.\nExpert-level experience generating GDSII/OAS layouts for MPW and dedicated full mask sets;\nExperience working in collaborative, team-based development environments, preferably with version control systems such as Git.\nExperience collaborating with internal teams and external partners across process integration, packaging, and fabrication.\nExperience using Python for component design, simulation, layout, and data analysis.\nAbility to work independently and collaboratively in a fast-paced, cross-disciplinary environment.\nStrong attention to detail and a rigorous, data-driven approach to problem solving.\nExcellent written and verbal communication skills.\nPreferred:\nBackground in developing superconducting single-photon detectors, circuits, and devices.\nExperience designing layouts for SNSPDs and other superconducting devices, with a strong understanding of their operating principles.\nExpertise in accounting for fabrication effects such as lithographic rounding, OPC/bias correction, and material non-uniformity during layout design.\nExperience with device-level modeling and simulation, such as COMSOL;\nExperience optimizing component performance through advanced layout techniques.\nBenefits and Compensation:\nBase salary will be determined according to location, experience, and internal benchmarks.\nEligible for equity.\nBenefits provided.\nOpportunity to work on advanced quantum computing hardware and fault-tolerant architecture.\nCollaborative and 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