{"id":2744717,"url":"https://alion.io/job/you-ag-silicon-physical-design-engineer-v","title":"Silicon Physical Design Engineer V","company":{"id":680198,"name":"Mindlance","domain":"mindlance.com","url":"https://alion.io/company/mindlance","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"SmartRecruiters","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":["US"],"hiring_countries_total":1,"salary":{"min":19200,"max":19200,"currency":"CAD","period":"year","gross":null,"usd_annual":13580},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Linux","optional":true},{"name":"Synopsys PrimePower","optional":true},{"name":"Synopsys Verdi","optional":true}],"status":"live","first_seen_at":"2026-10-16T22:05:53Z","employer_posted_date":null,"last_verified_at":"2026-10-16T22:05:53Z","board_verified":false,"closed_at":null,"days_open":11,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":11},"description":"This a Full Remote job, the offer is available from: United States, California (USA)\nJob Title : Silicon Physical Design Engineer V\nDesired Location (Remote/Onsite): Remote in PST time zome\nJob Description\nASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog.\nRESPONSIBILITIES\n- Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power).\n- Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis.\n- Correlate RTL-level power estimates against gate-level signoff power and explain deltas.\n- Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste.\n- Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle leakage).\n- Automate flows and reporting with TCL, Python, and Make-based build systems; integrate into regression/CI.\n- Document methodology and support design teams in interpreting results.\n- Perform PPA optimization with Fusion compiler.\n- Perform RTL and netlist level Power analysis\n- Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction\n- Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)\n- Implement some blocks at RTL and UPF\n- Ability to document and communicate clearly\nMINIMUM QUALIFICATIONS\n- 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer\n- Experience with power estimation tools and synthesis, some physical design\n- Knowledge of power trade-offs in design and back end implementation\n- Hands-on experience in scripting, data analysis\n- BS in Electrical Engineering/Computer Science or equivalent experience\nPREFERRED QUALIFICATIONS\n- Hands-on production experience with Synopsys (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence (Joules), PowrArtist\n- Ability to debug simulation-to-power flow issues end to end.\n- Strong scripting: TCL, Python and Excel based scripting and data-post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments.\n- Experience in low power design, tools and methodologies including power intent UPF specifications\nSilicon Power Characterization\n- Some power modeling/profiling experience at IP/SoC level\nCandidate Requirements\nMust-Have Skills\n1 Experience with power estimation tools and synthesis, some physical design\n2 Knowledge of power trade-offs in design and back end implementation\n3 Hands-on experience in scripting, data analysis\nNice-to-have Skills\n1 Hands-on experience with Synopsys PPRTL, PTPX/PrimePower, Verdi based power analysis and debug.\n2 Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle, leakage).\n3 Strong scripting: TCL, Python and Excel based scripting and data-post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments.\nYears of Experience: 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer\nDegrees/Certifications Required: BS in Electrical Engineering/Computer Science or equivalent experience.\nHow many rounds of interviews? 1-2 zoom interviews\nTypes of Interviews\n1. Power Analysis & Low Power Methodology\n2. Scripting (Optional)\nInterview Duration: 45 mins\nEEO:\n“Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of - Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”","description_format":"text","description_chars":3814,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-16T22:05:53Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 84 · green card filings: 6","filings_12m":84,"filings_prev_12m":51,"green_card_filings_12m":6,"median_offered_wage_usd":133167,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.476,"p_room":0.945,"age_days":11,"expected_fill_days":29,"reasons":["seen:11","agency","win:mid"],"computed_at":"2026-10-28T05:59:10Z"},"pay":{"stated_usd_annual":13580,"is_top_pay":false},"html_url":"https://alion.io/job/you-ag-silicon-physical-design-engineer-v","json_url":"https://alion.io/job/you-ag-silicon-physical-design-engineer-v.json","meta":{"generated_at":"2026-10-28T20:38:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28537,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":680198},"rest":"https://alion.io/mcp/rest/get_company?id=680198"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fyou-ag-silicon-physical-design-engineer-v"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fyou-ag-silicon-physical-design-engineer-v"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fyou-ag-silicon-physical-design-engineer-v"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/you-ag-silicon-physical-design-engineer-v\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fyou-ag-silicon-physical-design-engineer-v"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2744717}},{"tool":"search_jobs","arguments":{"company":"mindlance.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2744717},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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