Nicholas Mcsweenmanickchand
Hardware Engineer
Verilog
C++
Python
C
Real-time & Timing: 5/10
HDL & Circuit Logic: 5/10
Hardware-Software Interface: 4/10
Active 4 days ago
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Overview
Technical skills
Projects
Timeline
Roles
Overview
FPGA-focused digital logic engineer (senior) specializing in gate-level Ethernet switch and cut-through MAC design. The strongest proven skill is low-level RTL design and protocol-aware hardware interfacing as demonstrated by the combinational 8-bit CRC implementation (Individual_gate_level/FCS.v), GMII-facing TX MAC FSM (Individual_gate_level/TX_MAC.v) and CDC-aware FIFO (Individual_gate_level/FIFO.v). There is little or no evidence of testbenches, synthesis constraint files, CI/HIL validation or firmware/board bring-up in public code.
Phone
Technical skills
Verilog
C++
Python
C
Chips/EDA
FPGA
KiCad
Projects
Custom biometric wearable
I designed a custom biometric wearable from the ground up using an nRF52840, MAX30101 heart rate sensor, MPU6500 IMU, and a custom 4-layer PCB. I handled the schematic design, power system, USB-C protection, sensor integration, and PCB layout in KiCad, including the routing for the main power rails and USB differential pair. I’m also developing the embedded C/C++ firmware to communicate with the sensors over I2C and process the raw data into things like heart rate and step count. The project gave me a lot of hands-on experience with PCB design, embedded systems, power management, and debugging a complete hardware system.
C
C++
1G Custom Cut-Through Ethernet Switch
I designed and built a custom 1G cut-through Ethernet switch in Verilog based on IEEE 802.3. The main goal was to understand how Ethernet frames actually move through hardware instead of just treating networking as software. I implemented the forwarding logic so the switch could begin sending a frame before receiving the entire packet, while still checking the frame for errors and handling the data in parallel to keep latency low. The project gave me a much better understanding of Ethernet framing, digital hardware design, and how real networking hardware processes data.
Verilog
Xilinx Vivado
Timeline
Carleton University
Bachelor's Degree •
Electrical Engineering
Senior Embedded Engineer
Confidence: High FPGA Engineer
FPGA-focused digital logic engineer (senior) specializing in gate-level Ethernet switch and cut-through MAC design. The strongest proven skill is low-level RTL design and protocol-aware hardware interfacing as demonstrated by the combinational 8-bit CRC implementation (Individual_gate_level/FCS.v), GMII-facing TX MAC FSM (Individual_gate_level/TX_MAC.v) and CDC-aware FIFO (Individual_gate_level/FIFO.v). There is little or no evidence of testbenches, synthesis constraint files, CI/HIL validation or firmware/board bring-up in public code.
Embedded & Firmware
Low-level device code
Not evidenced in public code
Hardware-Software Interface
4/10
Connecting code to hardware
Concrete PHY-level interfacing and MAC/GMII signal handling with explicit packet framing and IPG timing; FIFO-to-arbiter data highway wiring shows practical HW-SW boundary thinking for PHY/MAC integration.
Evidence
Top_module.v: top-level GMII port declarations and wiring between PHY-facing ports and internal MAC/arbiters
Individual_gate_level/TX_MAC.v: TX MAC state machine, tx_en signal and enforced IPG timing for GMII/RGMII
Individual_gate_level/FIFO.v: first-word fall-through FIFO output and explicit empty flag used by downstream arbiter/PA
Resource Constraints
4/10
Working with limited resources
Resource-aware RTL choices such as a 2048-deep static FIFO, single-cycle 8-bit CRC combinational logic to avoid byte-shifting, and explicit counter widths show basic capacity planning and area/latency tradeoffs.
Evidence
Individual_gate_level/FIFO.v: tx_data_storage[2047:0], 12-bit writer/reader counters sized for FIFO depth
Individual_gate_level/FCS.v: combinational 8-bit-at-once CRC logic with comment about avoiding 8 shifts
Individual_gate_level/Ingress_FCS_Checker.v: use of 32-bit crcIn/reset residue handling indicating CRC resource reasoning
Real-time & Timing
5/10
Precise timing control
Timing-aware RTL: explicit IPG counter sized to 12 clock cycles at 125 MHz, CDC via Gray code in FIFO, and choice to compute CRC combinationally for cycle-budget reasons indicate thoughtful real-time and timing discipline.
Evidence
Individual_gate_level/TX_MAC.v: IPG_WAIT state and comment enforcing 12-cycle 96ns gap
Individual_gate_level/FIFO.v: gray code conversions and multi-register synchronization for CDC
Individual_gate_level/FCS.v and Ingress_FCS_Checker.v: combinational CRC math to process 8-bit bytes in a single cycle
HDL & Circuit Logic
5/10
Designing digital circuits
Solid HDL and circuit-level design evidence: manual combinational CRC generation, FSM-based MAC, EOF tagging and first-word-fall-through FIFO patterns; missing formal testbenches or constraint files but RTL appears hand-authored and non-trivial.
Evidence
Individual_gate_level/FCS.v: bit-level CRC equations for 32-bit CRC
Individual_gate_level/TX_MAC.v: clearly structured FSM with multiple states for preamble/SFD/data/FCS/IPG
Individual_gate_level/FIFO.v: EOF tagging, synchronous write/read domains and asynchronous read output (FWFT)
Reliability & On-device Testing
2/10
Testing on real hardware
Basic reliability measures exist at the RTL level (CRC checking, EOF tagging, empty flags), but there is no evidence of on-device testing, HIL/CI integration, formal verification runs, or deployment-level fault-recovery strategies.
Evidence
Individual_gate_level/Ingress_FCS_Checker.v: poison flag asserted on bad CRC residue
Individual_gate_level/FCS.v: poison input and rx_crc output pathways
Top_module.v: propagation of empty and allow_output signals between FIFO, PA and Arbiter
Expertise
FPGA & Digital Logic Design• Senior
Industries
Hardware• Senior
Telecommunications• Senior
Technologies
FPGA
Verilog• Senior
C
C++
KiCad
Recommendations
- Add thorough simulation testbenches (cycle-accurate packet-level tests) and regression using Verilator or similar to validate timing and CRC correctness.
- Provide synthesis constraints and synthesis-friendly scripts (XDC/timing constraints) and run reports to show timing closure for target FPGAs.
- Introduce formal checks or equivalence tests for the CRC and FIFO CDC (e.g., Symbiyosys/Verilator assertions or property checks).
- Add CI/HIL steps or small board bring-up notes that document PHY bring-up, signal integrity observations, or scope/log captures for real-world validation.
Repositories
The developer's experience in this domain has been verified based on AI analysis of the following repositories: