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Overview

Technologies

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Tech DNA
Python
Perl
SystemVerilog
PyTorch
UVM
LLM
AI/ML
Python
C++
AI Agents
LLM
DPO
Function Calling
LLM Evaluation
Post-training
PyTorch
Reinforcement Learning
Reward Modeling
RLAIF
RLHF
Tool Use
Other
Perl
SystemVerilog
Formal Verification
UVM
Stack modernity Modern AI adopter
72/100
How modern this stack is, based on technology relevance, AI adoption and the share of legacy tools.
In-demand technologies
Python 3 jobs Required
AI Agents 3 jobs Required
LLM 2 jobs Required
RLHF 1 job Required
Reinforcement Learning 1 job Required
Function Calling 1 job Required
PyTorch 1 job Required
DPO 1 job Required
Salary medians are calculated from this company's open jobs and compared with the market.
Stack changes
C++ Sep 2026
UVM Sep 2026
SystemVerilog Sep 2026
Perl Sep 2026
Formal Verification Sep 2026
Tool Use Sep 2026
RLHF Sep 2026
RLAIF Sep 2026
Technologies recently added to or removed from this company's stack - a signal of tech migrations and new initiatives.

Growth

Hiring Momentum
28/100
Slowing
Open positions
3
0 opened / 0 closed in 30 days
ATS activity
Every ~3 hours
09/12/2026
Hiring Focus
The percentage next to each role is its share of the company's job openings over the last 90 days; the arrow shows the shift versus the previous period.
Backend
67%
AI/ML
33%

Offices

Where the company hires and what each office is for
Cities
1
Hiring now
1
Countries
1
Busiest office
San Francisco
San Francisco United States
Engineering / R&D
3 open roles 100% engineering 1-10 est. staff
hires for Backend, AI/ML
seen since Aug 2024

Jobs

$125k – $297k per year (Estimated) • Equity • In office • Full-Time • Bachelor's Degree • San Francisco
Python
C++
AI Agents
LLM
Apply
$142k – $356k per year (Estimated) • Equity • In office • Full-Time • San Francisco
Python
RLHF
Reinforcement Learning
Function Calling
AI Agents
PyTorch
LLM
DPO
Post-training
LLM Evaluation
Tool Use
RLAIF
Reward Modeling
Apply
$97k – $219k per year (Estimated) • Equity • In office • Full-Time • 2+ years exp • San Francisco
Python
SystemVerilog
Perl
AI Agents
Chips/EDA
UVM
Formal Verification
Apply