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Overview
Expert-driven interdisciplinary deep-dives into the AI HW Infrastructure stack from first principles. Click to read Silicon Co-Design, by Chad, a Substack publication with thousands of subscribers.
News
Design Automation Conference 2026 - The Bottlenecks that Limit AI Use in Chip Design
AI is EDA is not as effective as pundits claim it to be, for now. Artour Levin, CVP AI Silicon Engineering, Microsoft, "EDA Opportunities in building high performance AI accelerators" DAC 2026 AI will not replace chip designers anytime soon. In fact, AI h
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A Comprehensive Overview of the AI Accelerator Landscape: From Digital to Analog Compute-in-Memory Architectures
Editors Note: (7/22/26): I trimmed the paywall to only paywall the scaling challenges with Analog CiM. This way, you can come away with a mental framework for the components of the Analog CiM. Compute-in-memory has emerged as a promising technology to ove
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A Comprehensive Deep Dive into High-Speed HBM5 Interconnect: Signal Integrity and Co-Design Challenges
While a lot of attention is being drawn to the current HBM4 shortage, this post will focused on the practical technical challenges in scaling HBM5 performance.I will discuss the following signal integrity and co-design challenges in HBM5 based on SK Hynix
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Solving AI's Beachfront Crisis for 200Gbps+ Interconnect: Marvell & Celestial AI's Optical Answer to Nvidia's NVLink
I'll be doing a deep dive into a few topics centered around Marvell/Celestial AI's Electro-Absorption (EAM) approach to scaling optical interconnects. The outline of my post is as follows: Motivation behind Optical InterconnectsAn Overview of GeSi Electro
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A Complete Deep Dive of NVIDIA DWDM Co-Packaged Optics for Scaling beyond 200Gbps
This post will be an advanced deep dive of a state-of-the-art co-packaged optical system based on NVIDIA's Dense-Wave Division Multiplexing (DWDM).This post is organized in the following sections:What is Dense-Wave Division Multiplexing?A complete archite
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