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AI is EDA is not as effective as pundits claim it to be, for now. Artour Levin, CVP AI Silicon Engineering, Microsoft, "EDA Opportunities in building high performance AI accelerators" DAC 2026 AI will not replace chip designers anytime soon. In fact, AI h

Editors Note: (7/22/26): I trimmed the paywall to only paywall the scaling challenges with Analog CiM. This way, you can come away with a mental framework for the components of the Analog CiM. Compute-in-memory has emerged as a promising technology to ove

While a lot of attention is being drawn to the current HBM4 shortage, this post will focused on the practical technical challenges in scaling HBM5 performance.I will discuss the following signal integrity and co-design challenges in HBM5 based on SK Hynix

I'll be doing a deep dive into a few topics centered around Marvell/Celestial AI's Electro-Absorption (EAM) approach to scaling optical interconnects. The outline of my post is as follows: Motivation behind Optical InterconnectsAn Overview of GeSi Electro

This post will be an advanced deep dive of a state-of-the-art co-packaged optical system based on NVIDIA's Dense-Wave Division Multiplexing (DWDM).This post is organized in the following sections:What is Dense-Wave Division Multiplexing?A complete archite

At ECTC 2026, TSMC noted that many package designers are being too aggressive with their package designs and that a lot of communication is needed to balance the design performance with the manufacturing and reliability constraints of the package. This po

In this post I'll build intuition of the key tradeoffs and constraints surrounding advanced packaging. I'll define each of the classifications at a high level (from 2D to 3.5D)Then I'll do a breakdown of each of the key options of a TSMC 2.5D CHIP on WAFE

Deep-Tech Semiconductor Analyst, MSEE. Educating engineers on the complete AI datacenter hardware stack from first principles.

In this post I discuss the following topics:Clear definitions of five buzzwords used in advanced packaging from John Lau's tutorial How Reliability is one of the biggest concerns for engineers on the floorThe Wild West of Co-packaged optics - Different CP

I want to take a moment in this post to reflect on the past five conferences I've attended, why I attended these, what I learned, and the advice I would give to engineers thinking of doing the same. Why ISSCC, DesignCon, APEC, ECTC, and DAC?I recently had